Files
android_kernel_xiaomi_sm8450/drivers/gpu/drm/msm
Archit Taneja b148928010 drm/msm/mdp5: Update mdp5_pipe_assign to spit out both planes
We currently call mdp5_pipe_assign() twice to assign the left and right
hwpipes for our drm_plane. When merging 2 hwpipes, there are a few
constraints that we need to keep in mind:

- Only the same types of SSPPs are preferred. I.e, a RGB pipe should
  be paired with another RGB pipe, VIG with VIG etc.
- The hwpipe staged on the left should have a higher priority than
  the hwpipe staged on the right. The priorities are as follows:
  VIG0 > VIG1 > VIG2 > VIG3
  RGB0 > RGB1 > RGB2 > RGB3
  DMA0 > DMA1

We can't apply these constraints easily if mdp5_pipe_assign() is
called twice. Update mdp5_pipe_assign() to find both hwpipes in
one go, and add the extra constraints needed.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28 14:02:58 -04:00
..
2017-10-28 11:01:33 -04:00
2017-10-28 11:01:33 -04:00
2017-04-08 06:59:31 -04:00
2014-01-09 14:44:06 -05:00