xiaomi-sm8450/android_kernel_xiaomi_sm8450
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android_kernel_xiaomi_sm8450/arch/mips/mm/c-r4k.c
Markos Chandras b5ad2c2193 MIPS: mm: scache: Add secondary cache support for MIPS R6 cores 
The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:31 +00:00

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