f7bcd4b6f6
The current hardware is not able to run with all cores enabled at a
cluster frequency superior at 1536MHz.
But the currently shipped u-boot for the platform still reports an OPP
table with possible DVFS frequency up to 2GHz, and will not change since
the off-tree linux tree supports limiting the OPPs with a kernel parameter.
A recent u-boot change reports the boot-time DVFS around 100MHz and
the default performance cpufreq governor sets the maximum frequency.
Previous version of u-boot reported to be already at the max OPP and
left the OPP as is.
Nevertheless, other governors like ondemand could setup the max frequency
and make the system crash.
This patch disables the DVFS clock and disables cpufreq.
Fixes: 70db166a2b ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
513 lines
10 KiB
Plaintext
513 lines
10 KiB
Plaintext
/*
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* Copyright (c) 2016 Andreas Färber
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "meson-gx.dtsi"
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#include <dt-bindings/gpio/meson-gxbb-gpio.h>
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#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
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#include <dt-bindings/clock/gxbb-clkc.h>
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#include <dt-bindings/clock/gxbb-aoclkc.h>
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#include <dt-bindings/reset/gxbb-aoclkc.h>
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/ {
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compatible = "amlogic,meson-gxbb";
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scpi {
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compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
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mboxes = <&mailbox 1 &mailbox 2>;
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shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
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scpi_clocks: clocks {
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compatible = "arm,scpi-clocks";
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scpi_dvfs: scpi_clocks@0 {
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compatible = "arm,scpi-dvfs-clocks";
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#clock-cells = <1>;
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clock-indices = <0>;
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clock-output-names = "vcpu";
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};
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};
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scpi_sensors: sensors {
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compatible = "arm,scpi-sensors";
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#thermal-sensor-cells = <1>;
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};
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};
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soc {
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usb0_phy: phy@c0000000 {
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compatible = "amlogic,meson-gxbb-usb2-phy";
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#phy-cells = <0>;
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reg = <0x0 0xc0000000 0x0 0x20>;
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resets = <&reset RESET_USB_OTG>;
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clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
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clock-names = "usb_general", "usb";
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status = "disabled";
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};
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usb1_phy: phy@c0000020 {
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compatible = "amlogic,meson-gxbb-usb2-phy";
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#phy-cells = <0>;
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reg = <0x0 0xc0000020 0x0 0x20>;
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resets = <&reset RESET_USB_OTG>;
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clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
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clock-names = "usb_general", "usb";
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status = "disabled";
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};
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sram: sram@c8000000 {
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compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
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reg = <0x0 0xc8000000 0x0 0x14000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0xc8000000 0x14000>;
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cpu_scp_lpri: scp-shmem@0 {
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compatible = "amlogic,meson-gxbb-scp-shmem";
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reg = <0x13000 0x400>;
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};
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cpu_scp_hpri: scp-shmem@200 {
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compatible = "amlogic,meson-gxbb-scp-shmem";
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reg = <0x13400 0x400>;
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};
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};
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usb0: usb@c9000000 {
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compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
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reg = <0x0 0xc9000000 0x0 0x40000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
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clock-names = "otg";
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phys = <&usb0_phy>;
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phy-names = "usb2-phy";
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dr_mode = "host";
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status = "disabled";
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};
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usb1: usb@c9100000 {
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compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
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reg = <0x0 0xc9100000 0x0 0x40000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
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clock-names = "otg";
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phys = <&usb1_phy>;
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phy-names = "usb2-phy";
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dr_mode = "host";
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status = "disabled";
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};
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};
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};
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&cpu0 {
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clocks = <&scpi_dvfs 0>;
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};
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&cpu1 {
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clocks = <&scpi_dvfs 0>;
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};
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&cpu2 {
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clocks = <&scpi_dvfs 0>;
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};
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&cpu3 {
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clocks = <&scpi_dvfs 0>;
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};
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&cbus {
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spifc: spi@8c80 {
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compatible = "amlogic,meson-gxbb-spifc";
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reg = <0x0 0x08c80 0x0 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkc CLKID_SPI>;
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status = "disabled";
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};
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};
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ðmac {
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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};
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&aobus {
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pinctrl_aobus: pinctrl@14 {
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compatible = "amlogic,meson-gxbb-aobus-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_ao: bank@14 {
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reg = <0x0 0x00014 0x0 0x8>,
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<0x0 0x0002c 0x0 0x4>,
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<0x0 0x00024 0x0 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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uart_ao_a_pins: uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
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function = "uart_ao";
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};
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};
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remote_input_ao_pins: remote_input_ao {
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mux {
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groups = "remote_input_ao";
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function = "remote_input_ao";
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};
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};
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i2c_ao_pins: i2c_ao {
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mux {
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groups = "i2c_sck_ao",
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"i2c_sda_ao";
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function = "i2c_ao";
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};
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};
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pwm_ao_a_3_pins: pwm_ao_a_3 {
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mux {
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groups = "pwm_ao_a_3";
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function = "pwm_ao_a_3";
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};
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};
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pwm_ao_a_6_pins: pwm_ao_a_6 {
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mux {
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groups = "pwm_ao_a_6";
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function = "pwm_ao_a_6";
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};
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};
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pwm_ao_a_12_pins: pwm_ao_a_12 {
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mux {
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groups = "pwm_ao_a_12";
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function = "pwm_ao_a_12";
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};
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};
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pwm_ao_b_pins: pwm_ao_b {
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mux {
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groups = "pwm_ao_b";
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function = "pwm_ao_b";
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};
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};
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};
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gxbb-aoclkc";
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reg = <0x0 0x00040 0x0 0x4>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pwm_ab_AO: pwm@550 {
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compatible = "amlogic,meson-gxbb-pwm";
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reg = <0x0 0x0550 0x0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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i2c_AO: i2c@500 {
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compatible = "amlogic,meson-gxbb-i2c";
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reg = <0x0 0x500 0x0 0x20>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkc CLKID_AO_I2C>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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&periphs {
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pinctrl_periphs: pinctrl@4b0 {
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compatible = "amlogic,meson-gxbb-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@4b0 {
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reg = <0x0 0x004b0 0x0 0x28>,
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<0x0 0x004e8 0x0 0x14>,
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<0x0 0x00120 0x0 0x14>,
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<0x0 0x00430 0x0 0x40>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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emmc_pins: emmc {
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mux {
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groups = "emmc_nand_d07",
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"emmc_cmd",
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"emmc_clk",
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"emmc_ds";
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function = "emmc";
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};
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};
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nor_pins: nor {
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mux {
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groups = "nor_d",
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"nor_q",
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"nor_c",
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"nor_cs";
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function = "nor";
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};
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};
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sdcard_pins: sdcard {
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mux {
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groups = "sdcard_d0",
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"sdcard_d1",
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"sdcard_d2",
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"sdcard_d3",
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"sdcard_cmd",
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"sdcard_clk";
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function = "sdcard";
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};
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};
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sdio_pins: sdio {
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mux {
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groups = "sdio_d0",
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"sdio_d1",
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"sdio_d2",
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"sdio_d3",
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"sdio_cmd",
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"sdio_clk";
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function = "sdio";
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};
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};
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sdio_irq_pins: sdio_irq {
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mux {
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groups = "sdio_irq";
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function = "sdio";
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};
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};
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uart_a_pins: uart_a {
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mux {
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groups = "uart_tx_a",
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"uart_rx_a";
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function = "uart_a";
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};
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};
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uart_b_pins: uart_b {
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mux {
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groups = "uart_tx_b",
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"uart_rx_b";
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function = "uart_b";
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};
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};
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uart_c_pins: uart_c {
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mux {
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groups = "uart_tx_c",
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"uart_rx_c";
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function = "uart_c";
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};
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};
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i2c_a_pins: i2c_a {
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mux {
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groups = "i2c_sck_a",
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"i2c_sda_a";
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function = "i2c_a";
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};
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};
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i2c_b_pins: i2c_b {
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mux {
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groups = "i2c_sck_b",
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"i2c_sda_b";
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function = "i2c_b";
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};
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};
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i2c_c_pins: i2c_c {
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mux {
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groups = "i2c_sck_c",
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"i2c_sda_c";
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function = "i2c_c";
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};
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};
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eth_rgmii_pins: eth-rgmii {
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mux {
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groups = "eth_mdio",
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"eth_mdc",
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"eth_clk_rx_clk",
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"eth_rx_dv",
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"eth_rxd0",
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"eth_rxd1",
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"eth_rxd2",
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"eth_rxd3",
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"eth_rgmii_tx_clk",
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"eth_tx_en",
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"eth_txd0",
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"eth_txd1",
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"eth_txd2",
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"eth_txd3";
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function = "eth";
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};
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};
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eth_rmii_pins: eth-rmii {
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mux {
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groups = "eth_mdio",
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"eth_mdc",
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"eth_clk_rx_clk",
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"eth_rx_dv",
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"eth_rxd0",
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"eth_rxd1",
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"eth_tx_en",
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"eth_txd0",
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"eth_txd1";
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function = "eth";
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};
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};
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pwm_a_x_pins: pwm_a_x {
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mux {
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groups = "pwm_a_x";
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function = "pwm_a_x";
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};
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};
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pwm_a_y_pins: pwm_a_y {
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mux {
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groups = "pwm_a_y";
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function = "pwm_a_y";
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};
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};
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pwm_b_pins: pwm_b {
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mux {
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groups = "pwm_b";
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function = "pwm_b";
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};
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};
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pwm_d_pins: pwm_d {
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mux {
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groups = "pwm_d";
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function = "pwm_d";
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};
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};
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pwm_e_pins: pwm_e {
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mux {
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groups = "pwm_e";
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function = "pwm_e";
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};
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};
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pwm_f_x_pins: pwm_f_x {
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mux {
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groups = "pwm_f_x";
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function = "pwm_f_x";
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};
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};
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pwm_f_y_pins: pwm_f_y {
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mux {
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groups = "pwm_f_y";
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function = "pwm_f_y";
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};
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};
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};
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};
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&hiubus {
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clkc: clock-controller@0 {
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compatible = "amlogic,gxbb-clkc";
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#clock-cells = <1>;
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reg = <0x0 0x0 0x0 0x3db>;
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};
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};
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&i2c_A {
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clocks = <&clkc CLKID_I2C>;
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};
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&i2c_B {
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clocks = <&clkc CLKID_I2C>;
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};
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&i2c_C {
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clocks = <&clkc CLKID_I2C>;
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};
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&sd_emmc_a {
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clocks = <&clkc CLKID_SD_EMMC_A>,
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<&xtal>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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};
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&sd_emmc_b {
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clocks = <&clkc CLKID_SD_EMMC_B>,
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<&xtal>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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};
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&sd_emmc_c {
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clocks = <&clkc CLKID_SD_EMMC_C>,
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<&xtal>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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};
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&vpu {
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compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
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};
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