ad68f8d3c2
For interrupts numbered after those of the interrupt controller, define their numbers based upon the number of interrupts provided by the SoC interrupt controller. This is in preparation for supporting newer Ingenic SoCs which provide more interrupts. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10143/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
62 lines
2.0 KiB
C
62 lines
2.0 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 IRQ definitions
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __ASM_MACH_JZ4740_IRQ_H__
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#define __ASM_MACH_JZ4740_IRQ_H__
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#define MIPS_CPU_IRQ_BASE 0
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#define JZ4740_IRQ_BASE 8
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#ifdef CONFIG_MACH_JZ4740
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# define NR_INTC_IRQS 32
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#endif
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/* 1st-level interrupts */
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#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
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#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
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#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
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#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
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#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
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#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
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#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
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#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
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#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
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#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
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#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
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#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
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#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
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#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
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#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
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#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
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#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
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#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
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#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
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#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
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#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
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#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
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#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
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/* 2nd-level interrupts */
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#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(NR_INTC_IRQS) + (x))
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#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
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#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))
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#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(NR_INTC_IRQS + 144)
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#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
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#endif
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