20499ed3c0
commit 9d67412f24cc3a2c05f35f7c856addb07a2960ce upstream.
iop32x is one of the last platforms to use IRQ 0, and this has apparently
stopped working in a 2014 cleanup without anyone noticing. This interrupt
is used for the DMA engine, so most likely this has not actually worked
in the past 7 years, but it's also not essential for using this board.
I'm splitting out this change from my GENERIC_IRQ_MULTI_HANDLER
conversion so it can be backported if anyone cares.
Fixes: a71b092a9c ("ARM: Convert handle_IRQ to use __handle_domain_irq")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[ardb: take +1 offset into account in mask/unmask and init as well]
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
32 lines
917 B
ArmAsm
32 lines
917 B
ArmAsm
/*
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* arch/arm/mach-iop32x/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for IOP32x-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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.macro get_irqnr_preamble, base, tmp
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mrc p15, 0, \tmp, c15, c1, 0
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orr \tmp, \tmp, #(1 << 6)
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mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
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mrc p15, 0, \tmp, c15, c1, 0
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mov \tmp, \tmp
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sub pc, pc, #4 @ cp_wait
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
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cmp \irqstat, #0
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clzne \irqnr, \irqstat
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rsbne \irqnr, \irqnr, #32
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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mrc p15, 0, \tmp1, c15, c1, 0
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ands \tmp2, \tmp1, #(1 << 6)
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bicne \tmp1, \tmp1, #(1 << 6)
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mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
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.endm
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