0ffb9f83e4
commit d3a5a68cff47f6eead84504c3c28376b85053242 upstream.
The address bits used to select the futex spinlock need to match those used in
the LWS code in syscall.S. The mask 0x3f8 only selects 7 bits. It should
select 8 bits.
This change fixes the glibc nptl/tst-cond24 and nptl/tst-cond25 tests.
Signed-off-by: John David Anglin <dave.anglin@bell.net>
Fixes: 53a42b6324 ("parisc: Switch to more fine grained lws locks")
Cc: stable@vger.kernel.org # 5.10+
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
124 lines
2.6 KiB
C
124 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_PARISC_FUTEX_H
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#define _ASM_PARISC_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/atomic.h>
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#include <asm/errno.h>
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/* The following has to match the LWS code in syscall.S. We have
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sixteen four-word locks. */
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static inline void
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_futex_spin_lock_irqsave(u32 __user *uaddr, unsigned long int *flags)
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{
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extern u32 lws_lock_start[];
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long index = ((long)uaddr & 0x7f8) >> 1;
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arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index];
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local_irq_save(*flags);
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arch_spin_lock(s);
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}
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static inline void
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_futex_spin_unlock_irqrestore(u32 __user *uaddr, unsigned long int *flags)
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{
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extern u32 lws_lock_start[];
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long index = ((long)uaddr & 0x7f8) >> 1;
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arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index];
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arch_spin_unlock(s);
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local_irq_restore(*flags);
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}
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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unsigned long int flags;
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int oldval, ret;
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u32 tmp;
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_futex_spin_lock_irqsave(uaddr, &flags);
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ret = -EFAULT;
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if (unlikely(get_user(oldval, uaddr) != 0))
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goto out_pagefault_enable;
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ret = 0;
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tmp = oldval;
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switch (op) {
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case FUTEX_OP_SET:
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tmp = oparg;
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break;
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case FUTEX_OP_ADD:
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tmp += oparg;
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break;
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case FUTEX_OP_OR:
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tmp |= oparg;
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break;
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case FUTEX_OP_ANDN:
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tmp &= ~oparg;
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break;
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case FUTEX_OP_XOR:
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tmp ^= oparg;
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break;
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default:
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ret = -ENOSYS;
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}
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if (ret == 0 && unlikely(put_user(tmp, uaddr) != 0))
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ret = -EFAULT;
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out_pagefault_enable:
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_futex_spin_unlock_irqrestore(uaddr, &flags);
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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u32 val;
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unsigned long flags;
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/* futex.c wants to do a cmpxchg_inatomic on kernel NULL, which is
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* our gateway page, and causes no end of trouble...
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*/
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if (uaccess_kernel() && !uaddr)
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return -EFAULT;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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/* HPPA has no cmpxchg in hardware and therefore the
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* best we can do here is use an array of locks. The
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* lock selected is based on a hash of the userspace
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* address. This should scale to a couple of CPUs.
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*/
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_futex_spin_lock_irqsave(uaddr, &flags);
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if (unlikely(get_user(val, uaddr) != 0)) {
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_futex_spin_unlock_irqrestore(uaddr, &flags);
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return -EFAULT;
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}
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if (val == oldval && unlikely(put_user(newval, uaddr) != 0)) {
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_futex_spin_unlock_irqrestore(uaddr, &flags);
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return -EFAULT;
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}
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*uval = val;
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_futex_spin_unlock_irqrestore(uaddr, &flags);
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return 0;
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}
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#endif /*__KERNEL__*/
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#endif /*_ASM_PARISC_FUTEX_H*/
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