98d9f30c82
powerpc has two different ways of matching PCI devices to their corresponding OF node (if any) for historical reasons. The ppc64 one does a scan looking for matching bus/dev/fn, while the ppc32 one does a scan looking only for matching dev/fn on each level in order to be agnostic to busses being renumbered (which Linux does on some platforms). This removes both and instead moves the matching code to the PCI core itself. It's the most logical place to do it: when a pci_dev is created, we know the parent and thus can do a single level scan for the matching device_node (if any). The benefit is that all archs now get the matching for free. There's one hook the arch might want to provide to match a PHB bus to its device node. A default weak implementation is provided that looks for the parent device device node, but it's not entirely reliable on powerpc for various reasons so powerpc provides its own. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
204 lines
5.8 KiB
C
204 lines
5.8 KiB
C
#ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
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#define _ASM_MICROBLAZE_PCI_BRIDGE_H
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#ifdef __KERNEL__
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/pci.h>
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#include <linux/list.h>
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#include <linux/ioport.h>
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struct device_node;
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enum {
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/* Force re-assigning all resources (ignore firmware
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* setup completely)
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*/
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PCI_REASSIGN_ALL_RSRC = 0x00000001,
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/* Re-assign all bus numbers */
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PCI_REASSIGN_ALL_BUS = 0x00000002,
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/* Do not try to assign, just use existing setup */
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PCI_PROBE_ONLY = 0x00000004,
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/* Don't bother with ISA alignment unless the bridge has
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* ISA forwarding enabled
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*/
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PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
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/* Enable domain numbers in /proc */
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PCI_ENABLE_PROC_DOMAINS = 0x00000010,
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/* ... except for domain 0 */
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PCI_COMPAT_DOMAIN_0 = 0x00000020,
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};
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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struct pci_bus *bus;
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char is_dynamic;
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struct device_node *dn;
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struct list_head list_node;
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struct device *parent;
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int first_busno;
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int last_busno;
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int self_busno;
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void __iomem *io_base_virt;
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resource_size_t io_base_phys;
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resource_size_t pci_io_size;
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/* Some machines (PReP) have a non 1:1 mapping of
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* the PCI memory space in the CPU bus space
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*/
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resource_size_t pci_mem_offset;
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/* Some machines have a special region to forward the ISA
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* "memory" cycles such as VGA memory regions. Left to 0
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* if unsupported
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*/
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resource_size_t isa_mem_phys;
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resource_size_t isa_mem_size;
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struct pci_ops *ops;
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unsigned int __iomem *cfg_addr;
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void __iomem *cfg_data;
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/*
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* Used for variants of PCI indirect handling and possible quirks:
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* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
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* EXT_REG - provides access to PCI-e extended registers
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* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
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* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
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* to determine which bus number to match on when generating type0
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* config cycles
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* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
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* hanging if we don't have link and try to do config cycles to
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* anything but the PHB. Only allow talking to the PHB if this is
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* set.
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* BIG_ENDIAN - cfg_addr is a big endian register
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* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
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* on the PLB4. Effectively disable MRM commands by setting this.
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*/
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#define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
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#define INDIRECT_TYPE_EXT_REG 0x00000002
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#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
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#define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
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#define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
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#define INDIRECT_TYPE_BROKEN_MRM 0x00000020
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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*/
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struct resource io_resource;
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struct resource mem_resources[3];
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int global_number; /* PCI domain number */
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};
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#ifdef CONFIG_PCI
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static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
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{
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return dev->dev.of_node;
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}
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static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
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{
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return bus->dev.of_node;
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}
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static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
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{
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return bus->sysdata;
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}
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static inline int isa_vaddr_is_ioport(void __iomem *address)
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{
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/* No specific ISA handling on ppc32 at this stage, it
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* all goes through PCI
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*/
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return 0;
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}
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#endif /* CONFIG_PCI */
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/* These are used for config access before all the PCI probing
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has been done. */
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extern int early_read_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 *val);
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extern int early_read_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 *val);
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extern int early_read_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 *val);
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extern int early_write_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 val);
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extern int early_write_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 val);
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extern int early_write_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 val);
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extern int early_find_capability(struct pci_controller *hose, int bus,
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int dev_fn, int cap);
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extern void setup_indirect_pci(struct pci_controller *hose,
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resource_size_t cfg_addr,
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resource_size_t cfg_data, u32 flags);
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/* Get the PCI host controller for an OF device */
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extern struct pci_controller *pci_find_hose_for_OF_device(
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struct device_node *node);
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/* Fill up host controller resources from the OF node */
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extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary);
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/* Allocate & free a PCI host bridge structure */
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extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
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extern void pcibios_free_controller(struct pci_controller *phb);
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extern void pcibios_setup_phb_resources(struct pci_controller *hose);
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#ifdef CONFIG_PCI
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extern unsigned int pci_flags;
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static inline void pci_set_flags(int flags)
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{
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pci_flags = flags;
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}
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static inline void pci_add_flags(int flags)
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{
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pci_flags |= flags;
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}
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static inline int pci_has_flag(int flag)
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{
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return pci_flags & flag;
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}
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extern struct list_head hose_list;
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extern int pcibios_vaddr_is_ioport(void __iomem *address);
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#else
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static inline int pcibios_vaddr_is_ioport(void __iomem *address)
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{
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return 0;
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}
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static inline void pci_set_flags(int flags) { }
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static inline void pci_add_flags(int flags) { }
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static inline int pci_has_flag(int flag)
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{
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return 0;
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}
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#endif /* CONFIG_PCI */
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#endif /* __KERNEL__ */
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#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
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