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8e8ec596e6c0144e2dd500a57ee23dde9684df46
android_kernel_xiaomi_sm8450/arch/powerpc/boot/dts/p4080ds.dts
Kim Phillips 8e8ec596e6 crypto: caam - Add support for the Freescale SEC4/CAAM 
The SEC4 supercedes the SEC2.x/3.x as Freescale's
Integrated Security Engine.  Its programming model is
incompatible with all prior versions of the SEC (talitos).

The SEC4 is also known as the Cryptographic Accelerator
and Assurance Module (CAAM); this driver is named caam.

This initial submission does not include support for Data Path
mode operation - AEAD descriptors are submitted via the job
ring interface, while the Queue Interface (QI) is enabled
for use by others.  Only AEAD algorithms are implemented
at this time, for use with IPsec.

Many thanks to the Freescale STC team for their contributions
to this driver.

Signed-off-by: Steve Cornelius <sec@pobox.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2011-03-27 10:45:16 +08:00

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/*
* P4080DS Device Tree Source
*
* Copyright 2009-2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "fsl,P4080DS";
compatible = "fsl,P4080DS";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ccsr = &soc;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
usb0 = &usb0;
usb1 = &usb1;
dma0 = &dma0;
dma1 = &dma1;
sdhc = &sdhc;
crypto = &crypto;
sec_jr0 = &sec_jr0;
sec_jr1 = &sec_jr1;
sec_jr2 = &sec_jr2;
sec_jr3 = &sec_jr3;
rtic_a = &rtic_a;
rtic_b = &rtic_b;
rtic_c = &rtic_c;
rtic_d = &rtic_d;
sec_mon = &sec_mon;
rio0 = &rapidio0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,4080@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
};
};
cpu1: PowerPC,4080@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
};
};
cpu2: PowerPC,4080@2 {
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
};
};
cpu3: PowerPC,4080@3 {
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
};
};
cpu4: PowerPC,4080@4 {
device_type = "cpu";
reg = <4>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
};
};
cpu5: PowerPC,4080@5 {
device_type = "cpu";
reg = <5>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
};
};
cpu6: PowerPC,4080@6 {
device_type = "cpu";
reg = <6>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
};
};
cpu7: PowerPC,4080@7 {
device_type = "cpu";
reg = <7>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
};
};
};
memory {
device_type = "memory";
};
soc: soc@ffe000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
corenet-law@0 {
compatible = "fsl,corenet-law";
reg = <0x0 0x1000>;
fsl,num-laws = <32>;
};
memory-controller@8000 {
compatible = "fsl,p4080-memory-controller";
reg = <0x8000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <0x12 2>;
};
memory-controller@9000 {
compatible = "fsl,p4080-memory-controller";
reg = <0x9000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <0x12 2>;
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
reg = <0x18000 0x1000>;
fsl,ccf-num-csdids = <32>;
fsl,ccf-num-snoopids = <32>;
};
iommu@20000 {
compatible = "fsl,p4080-pamu";
reg = <0x20000 0x10000>;
interrupts = <24 2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
dma0: dma@100300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
reg = <0x100300 0x4>;
ranges = <0x0 0x100100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <28 2>;
};
dma-channel@80 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <29 2>;
};
dma-channel@100 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <30 2>;
};
dma-channel@180 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <31 2>;
};
};
dma1: dma@101300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
reg = <0x101300 0x4>;
ranges = <0x0 0x101100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <32 2>;
};
dma-channel@80 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <33 2>;
};
dma-channel@100 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <34 2>;
};
dma-channel@180 {
compatible = "fsl,p4080-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <35 2>;
};
};
spi@110000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
reg = <0x110000 0x1000>;
interrupts = <53 0x2>;
interrupt-parent = <&mpic>;
fsl,espi-num-chipselects = <4>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
label = "u-boot";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@kernel {
label = "kernel";
reg = <0x00100000 0x00500000>;
read-only;
};
partition@dtb {
label = "dtb";
reg = <0x00600000 0x00100000>;
read-only;
};
partition@fs {
label = "file system";
reg = <0x00700000 0x00900000>;
};
};
};
sdhc: sdhc@114000 {
compatible = "fsl,p4080-esdhc", "fsl,esdhc";
reg = <0x114000 0x1000>;
interrupts = <48 2>;
interrupt-parent = <&mpic>;
voltage-ranges = <3300 3300>;
sdhci,auto-cmd12;
};
i2c@118000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x118000 0x100>;
interrupts = <38 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@118100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x118100 0x100>;
interrupts = <38 2>;
interrupt-parent = <&mpic>;
dfsrr;
eeprom@51 {
compatible = "at24,24c256";
reg = <0x51>;
};
eeprom@52 {
compatible = "at24,24c256";
reg = <0x52>;
};
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
interrupts = <0 0x1>;
interrupt-parent = <&mpic>;
};
};
i2c@119000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
compatible = "fsl-i2c";
reg = <0x119000 0x100>;
interrupts = <39 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@119100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <3>;
compatible = "fsl-i2c";
reg = <0x119100 0x100>;
interrupts = <39 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial0: serial@11c500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11c500 0x100>;
clock-frequency = <0>;
interrupts = <36 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@11c600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11c600 0x100>;
clock-frequency = <0>;
interrupts = <36 2>;
interrupt-parent = <&mpic>;
};
serial2: serial@11d500 {
cell-index = <2>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11d500 0x100>;
clock-frequency = <0>;
interrupts = <37 2>;
interrupt-parent = <&mpic>;
};
serial3: serial@11d600 {
cell-index = <3>;
device_type = "serial";
compatible = "ns16550";
reg = <0x11d600 0x100>;
clock-frequency = <0>;
interrupts = <37 2>;
interrupt-parent = <&mpic>;
};
gpio0: gpio@130000 {
compatible = "fsl,p4080-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2>;
interrupt-parent = <&mpic>;
#gpio-cells = <2>;
gpio-controller;
};
usb0: usb@210000 {
compatible = "fsl,p4080-usb2-mph",
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
reg = <0x210000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&mpic>;
interrupts = <44 0x2>;
phy_type = "ulpi";
};
usb1: usb@211000 {
compatible = "fsl,p4080-usb2-dr",
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
reg = <0x211000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&mpic>;
interrupts = <45 0x2>;
dr_mode = "host";
phy_type = "ulpi";
};
crypto: crypto@300000 {
compatible = "fsl,p4080-sec4.0", "fsl,sec4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
sec_jr0: jr@1000 {
compatible = "fsl,p4080-sec4.0-job-ring",
"fsl,sec4.0-job-ring";
reg = <0x1000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <88 2>;
};
sec_jr1: jr@2000 {
compatible = "fsl,p4080-sec4.0-job-ring",
"fsl,sec4.0-job-ring";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <89 2>;
};
sec_jr2: jr@3000 {
compatible = "fsl,p4080-sec4.0-job-ring",
"fsl,sec4.0-job-ring";
reg = <0x3000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <90 2>;
};
sec_jr3: jr@4000 {
compatible = "fsl,p4080-sec4.0-job-ring",
"fsl,sec4.0-job-ring";
reg = <0x4000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <91 2>;
};
rtic@6000 {
compatible = "fsl,p4080-sec4.0-rtic",
"fsl,sec4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,p4080-sec4.0-rtic-memory",
"fsl,sec4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,p4080-sec4.0-rtic-memory",
"fsl,sec4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,p4080-sec4.0-rtic-memory",
"fsl,sec4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,p4080-sec4.0-rtic-memory",
"fsl,sec4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,p4080-sec4.0-mon", "fsl,sec4.0-mon";
reg = <0x314000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <93 2>;
};
};
rapidio0: rapidio@ffe0c0000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "fsl,rapidio-delta";
reg = <0xf 0xfe0c0000 0 0x20000>;
ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
interrupt-parent = <&mpic>;
/* err_irq bell_outb_irq bell_inb_irq
msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
};
localbus@ffe124000 {
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
reg = <0xf 0xfe124000 0 0x1000>;
interrupts = <25 2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xf 0xe8000000 0x08000000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x08000000>;
bank-width = <2>;
device-width = <2>;
};
};
pci0: pcie@ffe200000 {
compatible = "fsl,p4080-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xfe200000 0 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
clock-frequency = <0x1fca055>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 40 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci1: pcie@ffe201000 {
compatible = "fsl,p4080-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xfe201000 0 0x1000>;
bus-range = <0 0xff>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
clock-frequency = <0x1fca055>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 41 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci2: pcie@ffe202000 {
compatible = "fsl,p4080-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xfe202000 0 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
clock-frequency = <0x1fca055>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 42 1
0000 0 0 2 &mpic 9 1
0000 0 0 3 &mpic 10 1
0000 0 0 4 &mpic 11 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
};
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