8b1c2ba274
As it turns out, all sdcc register writes must be delayed by at
least 3 core clock cycles for the writes to take effect. *sigh*
Also removes the 30us constant delay on clock enable in favor
of a 3 core clock delay.
Signed-off-by: San Mehat <san@google.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>