86ce85352f
All interrupt injection is now based on the VM ioctl KVM_IRQ_LINE. This
works semantically well for the GIC as we in fact raise/lower a line on
a machine component (the gic). The IOCTL uses the follwing struct.
struct kvm_irq_level {
union {
__u32 irq; /* GSI */
__s32 status; /* not used for KVM_IRQ_LEVEL */
};
__u32 level; /* 0 or 1 */
};
ARM can signal an interrupt either at the CPU level, or at the in-kernel irqchip
(GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for
specific cpus. The irq field is interpreted like this:
bits: | 31 ... 24 | 23 ... 16 | 15 ... 0 |
field: | irq_type | vcpu_index | irq_number |
The irq_type field has the following values:
- irq_type[0]: out-of-kernel GIC: irq_number 0 is IRQ, irq_number 1 is FIQ
- irq_type[1]: in-kernel GIC: SPI, irq_number between 32 and 1019 (incl.)
(the vcpu_index field is ignored)
- irq_type[2]: in-kernel GIC: PPI, irq_number between 16 and 31 (incl.)
The irq_number thus corresponds to the irq ID in as in the GICv2 specs.
This is documented in Documentation/kvm/api.txt.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
128 lines
3.8 KiB
C
128 lines
3.8 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_H__
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#define __ARM_KVM_H__
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#include <linux/types.h>
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#include <asm/ptrace.h>
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_IRQ_LINE
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
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#define KVM_ARM_SVC_sp svc_regs[0]
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#define KVM_ARM_SVC_lr svc_regs[1]
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#define KVM_ARM_SVC_spsr svc_regs[2]
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#define KVM_ARM_ABT_sp abt_regs[0]
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#define KVM_ARM_ABT_lr abt_regs[1]
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#define KVM_ARM_ABT_spsr abt_regs[2]
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#define KVM_ARM_UND_sp und_regs[0]
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#define KVM_ARM_UND_lr und_regs[1]
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#define KVM_ARM_UND_spsr und_regs[2]
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#define KVM_ARM_IRQ_sp irq_regs[0]
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#define KVM_ARM_IRQ_lr irq_regs[1]
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#define KVM_ARM_IRQ_spsr irq_regs[2]
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/* Valid only for fiq_regs in struct kvm_regs */
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#define KVM_ARM_FIQ_r8 fiq_regs[0]
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#define KVM_ARM_FIQ_r9 fiq_regs[1]
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#define KVM_ARM_FIQ_r10 fiq_regs[2]
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#define KVM_ARM_FIQ_fp fiq_regs[3]
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#define KVM_ARM_FIQ_ip fiq_regs[4]
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#define KVM_ARM_FIQ_sp fiq_regs[5]
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#define KVM_ARM_FIQ_lr fiq_regs[6]
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#define KVM_ARM_FIQ_spsr fiq_regs[7]
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struct kvm_regs {
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struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */
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__u32 svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
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__u32 abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
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__u32 und_regs[3]; /* SP_und, LR_und, SPSR_und */
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__u32 irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
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__u32 fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
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};
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/* Supported Processor Types */
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#define KVM_ARM_TARGET_CORTEX_A15 0
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#define KVM_ARM_NUM_TARGETS 1
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struct kvm_vcpu_init {
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__u32 target;
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__u32 features[7];
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};
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struct kvm_sregs {
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};
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struct kvm_fpu {
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};
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struct kvm_guest_debug_arch {
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};
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struct kvm_debug_exit_arch {
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};
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struct kvm_sync_regs {
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};
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struct kvm_arch_memory_slot {
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};
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
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#define KVM_REG_ARM_COPROC_SHIFT 16
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#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
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#define KVM_REG_ARM_32_OPC2_SHIFT 0
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#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
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#define KVM_REG_ARM_OPC1_SHIFT 3
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#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
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#define KVM_REG_ARM_CRM_SHIFT 7
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#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
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#define KVM_REG_ARM_32_CRN_SHIFT 11
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/* Normal registers are mapped as coprocessor 16. */
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#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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#define KVM_ARM_IRQ_TYPE_MASK 0xff
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#define KVM_ARM_IRQ_VCPU_SHIFT 16
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#define KVM_ARM_IRQ_VCPU_MASK 0xff
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#define KVM_ARM_IRQ_NUM_SHIFT 0
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#define KVM_ARM_IRQ_NUM_MASK 0xffff
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/* irq_type field */
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#define KVM_ARM_IRQ_TYPE_CPU 0
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#define KVM_ARM_IRQ_TYPE_SPI 1
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#define KVM_ARM_IRQ_TYPE_PPI 2
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/* out-of-kernel GIC cpu interrupt injection irq_number field */
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#define KVM_ARM_IRQ_CPU_IRQ 0
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#define KVM_ARM_IRQ_CPU_FIQ 1
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/* Highest supported SPI, from VGIC_NR_IRQS */
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#define KVM_ARM_IRQ_GIC_MAX 127
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#endif /* __ARM_KVM_H__ */
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