dfd437a257
Pull arm64 updates from Catalin Marinas:
- arm64 support for syscall emulation via PTRACE_SYSEMU{,_SINGLESTEP}
- Wire up VM_FLUSH_RESET_PERMS for arm64, allowing the core code to
manage the permissions of executable vmalloc regions more strictly
- Slight performance improvement by keeping softirqs enabled while
touching the FPSIMD/SVE state (kernel_neon_begin/end)
- Expose a couple of ARMv8.5 features to user (HWCAP): CondM (new
XAFLAG and AXFLAG instructions for floating point comparison flags
manipulation) and FRINT (rounding floating point numbers to integers)
- Re-instate ARM64_PSEUDO_NMI support which was previously marked as
BROKEN due to some bugs (now fixed)
- Improve parking of stopped CPUs and implement an arm64-specific
panic_smp_self_stop() to avoid warning on not being able to stop
secondary CPUs during panic
- perf: enable the ARM Statistical Profiling Extensions (SPE) on ACPI
platforms
- perf: DDR performance monitor support for iMX8QXP
- cache_line_size() can now be set from DT or ACPI/PPTT if provided to
cope with a system cache info not exposed via the CPUID registers
- Avoid warning on hardware cache line size greater than
ARCH_DMA_MINALIGN if the system is fully coherent
- arm64 do_page_fault() and hugetlb cleanups
- Refactor set_pte_at() to avoid redundant READ_ONCE(*ptep)
- Ignore ACPI 5.1 FADTs reported as 5.0 (infer from the
'arm_boot_flags' introduced in 5.1)
- CONFIG_RANDOMIZE_BASE now enabled in defconfig
- Allow the selection of ARM64_MODULE_PLTS, currently only done via
RANDOMIZE_BASE (and an erratum workaround), allowing modules to spill
over into the vmalloc area
- Make ZONE_DMA32 configurable
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (54 commits)
perf: arm_spe: Enable ACPI/Platform automatic module loading
arm_pmu: acpi: spe: Add initial MADT/SPE probing
ACPI/PPTT: Add function to return ACPI 6.3 Identical tokens
ACPI/PPTT: Modify node flag detection to find last IDENTICAL
x86/entry: Simplify _TIF_SYSCALL_EMU handling
arm64: rename dump_instr as dump_kernel_instr
arm64/mm: Drop [PTE|PMD]_TYPE_FAULT
arm64: Implement panic_smp_self_stop()
arm64: Improve parking of stopped CPUs
arm64: Expose FRINT capabilities to userspace
arm64: Expose ARMv8.5 CondM capability to userspace
arm64: defconfig: enable CONFIG_RANDOMIZE_BASE
arm64: ARM64_MODULES_PLTS must depend on MODULES
arm64: bpf: do not allocate executable memory
arm64/kprobes: set VM_FLUSH_RESET_PERMS on kprobe instruction pages
arm64/mm: wire up CONFIG_ARCH_HAS_SET_DIRECT_MAP
arm64: module: create module allocations without exec permissions
arm64: Allow user selection of ARM64_MODULE_PLTS
acpi/arm64: ignore 5.1 FADTs that are reported as 5.0
arm64: Allow selecting Pseudo-NMI again
...
168 lines
3.5 KiB
C
168 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm64/include/asm/arch_gicv3.h
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*
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* Copyright (C) 2015 ARM Ltd.
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*/
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#ifndef __ASM_ARCH_GICV3_H
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#define __ASM_ARCH_GICV3_H
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#include <asm/sysreg.h>
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#ifndef __ASSEMBLY__
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#include <linux/irqchip/arm-gic-common.h>
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#include <linux/stringify.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#define read_gicreg(r) read_sysreg_s(SYS_ ## r)
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#define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
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/*
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* Low-level accessors
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*
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* These system registers are 32 bits, but we make sure that the compiler
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* sets the GP register's most significant bits to 0 with an explicit cast.
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*/
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static inline void gic_write_eoir(u32 irq)
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{
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write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
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isb();
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}
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static inline void gic_write_dir(u32 irq)
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{
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write_sysreg_s(irq, SYS_ICC_DIR_EL1);
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isb();
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}
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static inline u64 gic_read_iar_common(void)
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{
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u64 irqstat;
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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dsb(sy);
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return irqstat;
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}
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/*
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* Cavium ThunderX erratum 23154
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*
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* The gicv3 of ThunderX requires a modified version for reading the
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* IAR status to ensure data synchronization (access to icc_iar1_el1
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* is not sync'ed before and after).
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*/
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static inline u64 gic_read_iar_cavium_thunderx(void)
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{
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u64 irqstat;
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nops(8);
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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nops(4);
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mb();
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return irqstat;
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}
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static inline void gic_write_ctlr(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_CTLR_EL1);
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isb();
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}
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static inline u32 gic_read_ctlr(void)
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{
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return read_sysreg_s(SYS_ICC_CTLR_EL1);
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}
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static inline void gic_write_grpen1(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
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}
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static inline u32 gic_read_sre(void)
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{
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return read_sysreg_s(SYS_ICC_SRE_EL1);
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}
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static inline void gic_write_sre(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_SRE_EL1);
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isb();
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}
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static inline void gic_write_bpr1(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_BPR1_EL1);
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}
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static inline u32 gic_read_pmr(void)
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{
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return read_sysreg_s(SYS_ICC_PMR_EL1);
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}
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static inline void gic_write_pmr(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_PMR_EL1);
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}
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static inline u32 gic_read_rpr(void)
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{
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return read_sysreg_s(SYS_ICC_RPR_EL1);
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}
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#define gic_read_typer(c) readq_relaxed(c)
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#define gic_write_irouter(v, c) writeq_relaxed(v, c)
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#define gic_read_lpir(c) readq_relaxed(c)
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#define gic_write_lpir(v, c) writeq_relaxed(v, c)
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#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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#define gits_read_baser(c) readq_relaxed(c)
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#define gits_write_baser(v, c) writeq_relaxed(v, c)
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#define gits_read_cbaser(c) readq_relaxed(c)
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#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
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#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
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#define gicr_read_propbaser(c) readq_relaxed(c)
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#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
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#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
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#define gicr_read_pendbaser(c) readq_relaxed(c)
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#define gits_write_vpropbaser(v, c) writeq_relaxed(v, c)
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#define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
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#define gits_read_vpendbaser(c) readq_relaxed(c)
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static inline bool gic_prio_masking_enabled(void)
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{
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return system_uses_irq_prio_masking();
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}
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static inline void gic_pmr_mask_irqs(void)
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{
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BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF |
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GIC_PRIO_PSR_I_SET));
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BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
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gic_write_pmr(GIC_PRIO_IRQOFF);
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}
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static inline void gic_arch_enable_irqs(void)
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{
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asm volatile ("msr daifclr, #2" : : : "memory");
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_GICV3_H */
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