854e80bcfd
Pull ARM devicetree updates from Arnd Bergmann:
"Most of the commits are for additional hardware support and minor
fixes for existing machines for all the usual platforms: qcom,
amlogic, at91, gemini, mediatek, ti, socfpga, i.mx, layerscape,
uniphier, rockchip, exynos, ux500, mvebu, tegra, stm32, renesas,
sunxi, broadcom, omap, and versatile.
The conversion of binding files to machine-readable yaml format
continues, along with fixes found during the validation. Andre
Przywara takes over maintainership for the old Calxeda Highbank
platform and provides a number of updates.
The OMAP2+ platforms see a continued move from platform data into dts
files, for many devices that relied on a mix of auxiliary data in
addition to the DT description
A moderate number of new SoCs and machines are added, here is a full
list:
- Two new Qualcomm SoCs with their evaluation boards: Snapdragon 865
(SM8250) is the current high-end phone chip, and IPQ6018 is a new
WiFi-6 router chip.
- Mediatek MT8516 application processor SoC for voice assistants,
along with the "pumpkin" development board
- NXP i.MX8M Plus SoC, a variant of the popular i.MX8M, along with an
evaluation board.
- Kontron "sl28" board family based on NXP LS1028A
- Eleven variations of the new i.MX6 TechNexion Pico board, combining
the "dwarf", "hobbit", "nymph" and "pi" baseboards with i.MX6/i.MX7
SoM carriers
- Three additional variants of the Toradex Colibri board family, all
based on versions of the NXP i.MX7.
- The Pinebook Pro laptop based on Rockchip RK3399
- Samsung S7710 Galaxy Xcover 2, a 2013 vintage Android phone based
on the ST-Ericsson u8500 platform
- DH Electronics DHCOM SoM and PDK2 rev. 400 carrier based on
STMicroelectronics stm32mp157
- Renesas M3ULCB starter kit for R-Car M3-W+
- Hoperun HiHope development board with Renesas RZ/G2M
- Pine64 PineTab tablet and PinePhone phone, both based on Allwinner
A64
- Linutronix Testbox v2 for the Lamobo R1 router, based on Allwinner
A20
- PocketBook Touch Lux 3 ebook reader, based on Allwinner A13"
* tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (520 commits)
ARM: dts: ux500: Fix missing node renames
arm64: dts: Revert "specify console via command line"
MAINTAINERS: Update Calxeda Highbank maintainership
arm: dts: calxeda: Group port-phys and sgpio-gpio items
arm: dts: calxeda: Fix interrupt grouping
arm: dts: calxeda: Provide UART clock
arm: dts: calxeda: Basic DT file fixes
arm64: dts: specify console via command line
ARM: dts: at91: sama5d27_wlsom1_ek: add USB device node
ARM: dts: gemini: Add thermal zone to DIR-685
ARM: dts: gemini: Rename IDE nodes
ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodes
arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes
arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node
arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC
arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0
arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC
arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes
arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node
arm64: dts: khadas-vim3: add SPIFC controller node
...
236 lines
7.4 KiB
C
236 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2018-2019 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
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#define __DT_BINDINGS_CLOCK_IMX8MN_H
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#define IMX8MN_CLK_DUMMY 0
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#define IMX8MN_CLK_32K 1
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#define IMX8MN_CLK_24M 2
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#define IMX8MN_OSC_HDMI_CLK 3
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#define IMX8MN_CLK_EXT1 4
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#define IMX8MN_CLK_EXT2 5
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#define IMX8MN_CLK_EXT3 6
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#define IMX8MN_CLK_EXT4 7
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#define IMX8MN_AUDIO_PLL1_REF_SEL 8
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#define IMX8MN_AUDIO_PLL2_REF_SEL 9
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#define IMX8MN_VIDEO_PLL1_REF_SEL 10
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#define IMX8MN_DRAM_PLL_REF_SEL 11
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#define IMX8MN_GPU_PLL_REF_SEL 12
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#define IMX8MN_VPU_PLL_REF_SEL 13
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#define IMX8MN_ARM_PLL_REF_SEL 14
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#define IMX8MN_SYS_PLL1_REF_SEL 15
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#define IMX8MN_SYS_PLL2_REF_SEL 16
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#define IMX8MN_SYS_PLL3_REF_SEL 17
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#define IMX8MN_AUDIO_PLL1 18
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#define IMX8MN_AUDIO_PLL2 19
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#define IMX8MN_VIDEO_PLL1 20
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#define IMX8MN_DRAM_PLL 21
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#define IMX8MN_GPU_PLL 22
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#define IMX8MN_VPU_PLL 23
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#define IMX8MN_ARM_PLL 24
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#define IMX8MN_SYS_PLL1 25
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#define IMX8MN_SYS_PLL2 26
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#define IMX8MN_SYS_PLL3 27
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#define IMX8MN_AUDIO_PLL1_BYPASS 28
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#define IMX8MN_AUDIO_PLL2_BYPASS 29
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#define IMX8MN_VIDEO_PLL1_BYPASS 30
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#define IMX8MN_DRAM_PLL_BYPASS 31
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#define IMX8MN_GPU_PLL_BYPASS 32
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#define IMX8MN_VPU_PLL_BYPASS 33
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#define IMX8MN_ARM_PLL_BYPASS 34
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#define IMX8MN_SYS_PLL1_BYPASS 35
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#define IMX8MN_SYS_PLL2_BYPASS 36
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#define IMX8MN_SYS_PLL3_BYPASS 37
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#define IMX8MN_AUDIO_PLL1_OUT 38
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#define IMX8MN_AUDIO_PLL2_OUT 39
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#define IMX8MN_VIDEO_PLL1_OUT 40
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#define IMX8MN_DRAM_PLL_OUT 41
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#define IMX8MN_GPU_PLL_OUT 42
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#define IMX8MN_VPU_PLL_OUT 43
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#define IMX8MN_ARM_PLL_OUT 44
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#define IMX8MN_SYS_PLL1_OUT 45
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#define IMX8MN_SYS_PLL2_OUT 46
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#define IMX8MN_SYS_PLL3_OUT 47
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#define IMX8MN_SYS_PLL1_40M 48
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#define IMX8MN_SYS_PLL1_80M 49
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#define IMX8MN_SYS_PLL1_100M 50
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#define IMX8MN_SYS_PLL1_133M 51
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#define IMX8MN_SYS_PLL1_160M 52
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#define IMX8MN_SYS_PLL1_200M 53
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#define IMX8MN_SYS_PLL1_266M 54
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#define IMX8MN_SYS_PLL1_400M 55
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#define IMX8MN_SYS_PLL1_800M 56
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#define IMX8MN_SYS_PLL2_50M 57
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#define IMX8MN_SYS_PLL2_100M 58
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#define IMX8MN_SYS_PLL2_125M 59
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#define IMX8MN_SYS_PLL2_166M 60
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#define IMX8MN_SYS_PLL2_200M 61
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#define IMX8MN_SYS_PLL2_250M 62
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#define IMX8MN_SYS_PLL2_333M 63
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#define IMX8MN_SYS_PLL2_500M 64
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#define IMX8MN_SYS_PLL2_1000M 65
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/* CORE CLOCK ROOT */
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#define IMX8MN_CLK_A53_SRC 66
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#define IMX8MN_CLK_GPU_CORE_SRC 67
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#define IMX8MN_CLK_GPU_SHADER_SRC 68
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#define IMX8MN_CLK_A53_CG 69
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#define IMX8MN_CLK_GPU_CORE_CG 70
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#define IMX8MN_CLK_GPU_SHADER_CG 71
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#define IMX8MN_CLK_A53_DIV 72
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#define IMX8MN_CLK_GPU_CORE_DIV 73
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#define IMX8MN_CLK_GPU_SHADER_DIV 74
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/* BUS CLOCK ROOT */
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#define IMX8MN_CLK_MAIN_AXI 75
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#define IMX8MN_CLK_ENET_AXI 76
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#define IMX8MN_CLK_NAND_USDHC_BUS 77
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#define IMX8MN_CLK_DISP_AXI 78
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#define IMX8MN_CLK_DISP_APB 79
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#define IMX8MN_CLK_USB_BUS 80
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#define IMX8MN_CLK_GPU_AXI 81
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#define IMX8MN_CLK_GPU_AHB 82
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#define IMX8MN_CLK_NOC 83
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#define IMX8MN_CLK_AHB 84
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#define IMX8MN_CLK_AUDIO_AHB 85
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/* IPG CLOCK ROOT */
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#define IMX8MN_CLK_IPG_ROOT 86
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#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
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/* IP */
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#define IMX8MN_CLK_DRAM_CORE 88
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#define IMX8MN_CLK_DRAM_ALT 89
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#define IMX8MN_CLK_DRAM_APB 90
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#define IMX8MN_CLK_DRAM_ALT_ROOT 91
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#define IMX8MN_CLK_DISP_PIXEL 92
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#define IMX8MN_CLK_SAI2 93
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#define IMX8MN_CLK_SAI3 94
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#define IMX8MN_CLK_SAI5 95
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#define IMX8MN_CLK_SAI6 96
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#define IMX8MN_CLK_SPDIF1 97
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#define IMX8MN_CLK_ENET_REF 98
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#define IMX8MN_CLK_ENET_TIMER 99
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#define IMX8MN_CLK_ENET_PHY_REF 100
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#define IMX8MN_CLK_NAND 101
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#define IMX8MN_CLK_QSPI 102
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#define IMX8MN_CLK_USDHC1 103
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#define IMX8MN_CLK_USDHC2 104
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#define IMX8MN_CLK_I2C1 105
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#define IMX8MN_CLK_I2C2 106
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#define IMX8MN_CLK_I2C3 107
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#define IMX8MN_CLK_I2C4 108
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#define IMX8MN_CLK_UART1 109
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#define IMX8MN_CLK_UART2 110
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#define IMX8MN_CLK_UART3 111
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#define IMX8MN_CLK_UART4 112
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#define IMX8MN_CLK_USB_CORE_REF 113
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#define IMX8MN_CLK_USB_PHY_REF 114
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#define IMX8MN_CLK_ECSPI1 115
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#define IMX8MN_CLK_ECSPI2 116
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#define IMX8MN_CLK_PWM1 117
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#define IMX8MN_CLK_PWM2 118
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#define IMX8MN_CLK_PWM3 119
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#define IMX8MN_CLK_PWM4 120
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#define IMX8MN_CLK_WDOG 121
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#define IMX8MN_CLK_WRCLK 122
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#define IMX8MN_CLK_CLKO1 123
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#define IMX8MN_CLK_CLKO2 124
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#define IMX8MN_CLK_DSI_CORE 125
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#define IMX8MN_CLK_DSI_PHY_REF 126
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#define IMX8MN_CLK_DSI_DBI 127
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#define IMX8MN_CLK_USDHC3 128
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#define IMX8MN_CLK_CAMERA_PIXEL 129
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#define IMX8MN_CLK_CSI1_PHY_REF 130
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#define IMX8MN_CLK_CSI2_PHY_REF 131
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#define IMX8MN_CLK_CSI2_ESC 132
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#define IMX8MN_CLK_ECSPI3 133
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#define IMX8MN_CLK_PDM 134
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#define IMX8MN_CLK_SAI7 135
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#define IMX8MN_CLK_ECSPI1_ROOT 136
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#define IMX8MN_CLK_ECSPI2_ROOT 137
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#define IMX8MN_CLK_ECSPI3_ROOT 138
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#define IMX8MN_CLK_ENET1_ROOT 139
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#define IMX8MN_CLK_GPIO1_ROOT 140
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#define IMX8MN_CLK_GPIO2_ROOT 141
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#define IMX8MN_CLK_GPIO3_ROOT 142
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#define IMX8MN_CLK_GPIO4_ROOT 143
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#define IMX8MN_CLK_GPIO5_ROOT 144
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#define IMX8MN_CLK_I2C1_ROOT 145
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#define IMX8MN_CLK_I2C2_ROOT 146
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#define IMX8MN_CLK_I2C3_ROOT 147
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#define IMX8MN_CLK_I2C4_ROOT 148
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#define IMX8MN_CLK_MU_ROOT 149
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#define IMX8MN_CLK_OCOTP_ROOT 150
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#define IMX8MN_CLK_PWM1_ROOT 151
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#define IMX8MN_CLK_PWM2_ROOT 152
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#define IMX8MN_CLK_PWM3_ROOT 153
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#define IMX8MN_CLK_PWM4_ROOT 154
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#define IMX8MN_CLK_QSPI_ROOT 155
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#define IMX8MN_CLK_NAND_ROOT 156
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#define IMX8MN_CLK_SAI2_ROOT 157
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#define IMX8MN_CLK_SAI2_IPG 158
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#define IMX8MN_CLK_SAI3_ROOT 159
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#define IMX8MN_CLK_SAI3_IPG 160
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#define IMX8MN_CLK_SAI5_ROOT 161
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#define IMX8MN_CLK_SAI5_IPG 162
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#define IMX8MN_CLK_SAI6_ROOT 163
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#define IMX8MN_CLK_SAI6_IPG 164
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#define IMX8MN_CLK_SAI7_ROOT 165
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#define IMX8MN_CLK_SAI7_IPG 166
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#define IMX8MN_CLK_SDMA1_ROOT 167
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#define IMX8MN_CLK_SDMA2_ROOT 168
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#define IMX8MN_CLK_UART1_ROOT 169
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#define IMX8MN_CLK_UART2_ROOT 170
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#define IMX8MN_CLK_UART3_ROOT 171
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#define IMX8MN_CLK_UART4_ROOT 172
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#define IMX8MN_CLK_USB1_CTRL_ROOT 173
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#define IMX8MN_CLK_USDHC1_ROOT 174
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#define IMX8MN_CLK_USDHC2_ROOT 175
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#define IMX8MN_CLK_WDOG1_ROOT 176
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#define IMX8MN_CLK_WDOG2_ROOT 177
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#define IMX8MN_CLK_WDOG3_ROOT 178
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#define IMX8MN_CLK_GPU_BUS_ROOT 179
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#define IMX8MN_CLK_ASRC_ROOT 180
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#define IMX8MN_CLK_GPU3D_ROOT 181
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#define IMX8MN_CLK_PDM_ROOT 182
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#define IMX8MN_CLK_PDM_IPG 183
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#define IMX8MN_CLK_DISP_AXI_ROOT 184
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#define IMX8MN_CLK_DISP_APB_ROOT 185
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#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
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#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
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#define IMX8MN_CLK_USDHC3_ROOT 188
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#define IMX8MN_CLK_SDMA3_ROOT 189
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#define IMX8MN_CLK_TMU_ROOT 190
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#define IMX8MN_CLK_ARM 191
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#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
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#define IMX8MN_CLK_GPU_CORE_ROOT 193
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#define IMX8MN_CLK_GIC 194
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#define IMX8MN_SYS_PLL1_40M_CG 195
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#define IMX8MN_SYS_PLL1_80M_CG 196
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#define IMX8MN_SYS_PLL1_100M_CG 197
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#define IMX8MN_SYS_PLL1_133M_CG 198
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#define IMX8MN_SYS_PLL1_160M_CG 199
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#define IMX8MN_SYS_PLL1_200M_CG 200
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#define IMX8MN_SYS_PLL1_266M_CG 201
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#define IMX8MN_SYS_PLL1_400M_CG 202
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#define IMX8MN_SYS_PLL2_50M_CG 203
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#define IMX8MN_SYS_PLL2_100M_CG 204
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#define IMX8MN_SYS_PLL2_125M_CG 205
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#define IMX8MN_SYS_PLL2_166M_CG 206
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#define IMX8MN_SYS_PLL2_200M_CG 207
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#define IMX8MN_SYS_PLL2_250M_CG 208
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#define IMX8MN_SYS_PLL2_333M_CG 209
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#define IMX8MN_SYS_PLL2_500M_CG 210
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#define IMX8MN_CLK_SNVS_ROOT 211
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#define IMX8MN_CLK_END 212
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#endif
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