xiaomi-sm8450/android_kernel_xiaomi_sm8450
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84667a416d42c8516468f4ef7a577296fbfd167d
android_kernel_xiaomi_sm8450/drivers/pci/controller/dwc
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Rob Herring 84667a416d PCI: dwc/tegra: Use common Designware port logic register definitions 
The Tegra driver has its own defines for common Designware Port Logic
registers. Convert it to use the standard register definitions.

Link: https://lore.kernel.org/r/20200821035420.380495-32-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org
2020-09-08 16:37:02 +01:00
..
Kconfig
Merge branch 'remotes/lorenzo/pci/dwc'
2020-06-04 12:59:15 -05:00
Makefile
PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver
2020-06-04 10:03:18 +01:00
pci-dra7xx.c
PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
2020-09-08 16:37:02 +01:00
pci-exynos.c
PCI: dwc: exynos: Use pci_ops for root config space accessors
2020-09-08 16:37:02 +01:00
pci-imx6.c
PCI: dwc/imx6: Use common PCI register definitions
2020-09-08 16:37:02 +01:00
pci-keystone.c
PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
2020-09-08 16:37:02 +01:00
pci-layerscape-ep.c
PCI: Add PCI_STD_NUM_BARS for the number of standard BARs
2019-10-14 10:22:26 -05:00
pci-layerscape.c
PCI: layerscape: Add LS1028a support
2019-11-08 10:45:00 +00:00
pci-meson.c
PCI: dwc/meson: Rework PCI config and DW port logic register accesses
2020-09-08 16:37:02 +01:00
pcie-al.c
PCI: dwc: Remove storing of PCI resources
2020-09-08 16:37:02 +01:00
pcie-armada8k.c
Merge branch 'pci/irq-error'
2020-08-05 18:24:22 -05:00
pcie-artpec6.c
PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
2020-09-08 16:37:02 +01:00
pcie-designware-ep.c
PCI: designware-ep: Fix the Header Type check
2020-09-07 10:25:22 +01:00
pcie-designware-host.c
PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
2020-09-08 16:37:02 +01:00
pcie-designware-plat.c
PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
2020-09-08 16:37:02 +01:00
pcie-designware.c
PCI: dwc: Add a 'num_lanes' field to struct dw_pcie
2020-09-08 16:37:08 +01:00
pcie-designware.h
PCI: dwc/tegra: Use common Designware port logic register definitions
2020-09-08 16:37:02 +01:00
pcie-hisi.c
PCI: dwc: hisi: Remove non-ECAM HiSilicon hip05/hip06 driver
2020-07-27 17:06:32 +01:00
pcie-histb.c
PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
2020-09-08 16:37:02 +01:00
pcie-intel-gw.c
PCI: dwc: Convert to devm_platform_ioremap_resource_byname()
2020-07-17 17:15:08 +01:00
pcie-kirin.c
PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
2020-09-08 16:37:02 +01:00
pcie-qcom.c
PCI: dwc/qcom: Use common PCI register definitions
2020-09-08 16:37:02 +01:00
pcie-spear13xx.c
PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
2020-09-08 16:37:02 +01:00
pcie-tegra194.c
PCI: dwc/tegra: Use common Designware port logic register definitions
2020-09-08 16:37:02 +01:00
pcie-uniphier-ep.c
PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver
2020-06-04 10:03:18 +01:00
pcie-uniphier.c
PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
2020-09-08 16:37:02 +01:00