7fec1b57b8
Since the ASIDs must be unique to an mm across all the CPUs in a system, the __new_context() function needs to broadcast a context reset event to all the CPUs during ASID allocation if a roll-over occurred. Such IPIs cannot be issued with interrupts disabled and ARM had to define __ARCH_WANT_INTERRUPTS_ON_CTXSW. This patch changes the check_context() function to check_and_switch_context() called from switch_mm(). In case of ASID-capable CPUs (ARMv6 onwards), if a new ASID is needed and the interrupts are disabled, it defers the __new_context() and cpu_switch_mm() calls to the post-lock switch hook where the interrupts are enabled. Setting the reserved TTBR0 was also moved to check_and_switch_context() from cpu_v7_switch_mm(). Reviewed-by: Will Deacon <will.deacon@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Frank Rowand <frank.rowand@am.sony.com> Tested-by: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
47 lines
955 B
C
47 lines
955 B
C
#ifndef __ARM_MMU_H
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#define __ARM_MMU_H
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#ifdef CONFIG_MMU
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typedef struct {
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#ifdef CONFIG_CPU_HAS_ASID
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unsigned int id;
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raw_spinlock_t id_lock;
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#endif
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unsigned int kvm_seq;
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} mm_context_t;
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#ifdef CONFIG_CPU_HAS_ASID
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#define ASID(mm) ((mm)->context.id & 255)
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/* init_mm.context.id_lock should be initialized. */
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#define INIT_MM_CONTEXT(name) \
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.context.id_lock = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
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#else
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#define ASID(mm) (0)
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#endif
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#else
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/*
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* From nommu.h:
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* Copyright (C) 2002, David McCullough <davidm@snapgear.com>
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* modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
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*/
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typedef struct {
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unsigned long end_brk;
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} mm_context_t;
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#endif
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/*
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* switch_mm() may do a full cache flush over the context switch,
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* so enable interrupts over the context switch to avoid high
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* latency.
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*/
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#ifndef CONFIG_CPU_HAS_ASID
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#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
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#endif
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#endif
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