7c732cba3d
The e500v1 doesn't implement the MAS7, so we should avoid to access this register on that implementations. In the current kernel, the access to MAS7 are protected by either CONFIG_PHYS_64BIT or MMU_FTR_BIG_PHYS. Since some code are executed before the code patching, we have to use CONFIG_PHYS_64BIT in these cases. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
/*
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* PPC Huge TLB Page Support for Book3E MMU
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*
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* Copyright (C) 2009 David Gibson, IBM Corporation.
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* Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
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*
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*/
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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static inline int mmu_get_tsize(int psize)
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{
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return mmu_psize_defs[psize].enc;
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}
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static inline int book3e_tlb_exists(unsigned long ea, unsigned long pid)
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{
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int found = 0;
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mtspr(SPRN_MAS6, pid << 16);
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if (mmu_has_feature(MMU_FTR_USE_TLBRSRV)) {
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asm volatile(
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"li %0,0\n"
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"tlbsx. 0,%1\n"
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"bne 1f\n"
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"li %0,1\n"
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"1:\n"
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: "=&r"(found) : "r"(ea));
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} else {
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asm volatile(
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"tlbsx 0,%1\n"
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"mfspr %0,0x271\n"
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"srwi %0,%0,31\n"
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: "=&r"(found) : "r"(ea));
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}
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return found;
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}
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void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
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pte_t pte)
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{
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unsigned long mas1, mas2;
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u64 mas7_3;
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unsigned long psize, tsize, shift;
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unsigned long flags;
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struct mm_struct *mm;
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#ifdef CONFIG_PPC_FSL_BOOK3E
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int index, ncams;
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#endif
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if (unlikely(is_kernel_addr(ea)))
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return;
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mm = vma->vm_mm;
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#ifdef CONFIG_PPC_MM_SLICES
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psize = get_slice_psize(mm, ea);
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tsize = mmu_get_tsize(psize);
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shift = mmu_psize_defs[psize].shift;
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#else
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psize = vma_mmu_pagesize(vma);
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shift = __ilog2(psize);
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tsize = shift - 10;
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#endif
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/*
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* We can't be interrupted while we're setting up the MAS
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* regusters or after we've confirmed that no tlb exists.
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*/
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local_irq_save(flags);
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if (unlikely(book3e_tlb_exists(ea, mm->context.id))) {
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local_irq_restore(flags);
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return;
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}
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#ifdef CONFIG_PPC_FSL_BOOK3E
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ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
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/* We have to use the CAM(TLB1) on FSL parts for hugepages */
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index = __get_cpu_var(next_tlbcam_idx);
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mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1));
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/* Just round-robin the entries and wrap when we hit the end */
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if (unlikely(index == ncams - 1))
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__get_cpu_var(next_tlbcam_idx) = tlbcam_index;
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else
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__get_cpu_var(next_tlbcam_idx)++;
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#endif
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mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize);
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mas2 = ea & ~((1UL << shift) - 1);
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mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
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mas7_3 = (u64)pte_pfn(pte) << PAGE_SHIFT;
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mas7_3 |= (pte_val(pte) >> PTE_BAP_SHIFT) & MAS3_BAP_MASK;
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if (!pte_dirty(pte))
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mas7_3 &= ~(MAS3_SW|MAS3_UW);
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mtspr(SPRN_MAS1, mas1);
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mtspr(SPRN_MAS2, mas2);
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if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) {
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mtspr(SPRN_MAS7_MAS3, mas7_3);
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} else {
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if (mmu_has_feature(MMU_FTR_BIG_PHYS))
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mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
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mtspr(SPRN_MAS3, lower_32_bits(mas7_3));
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}
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asm volatile ("tlbwe");
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local_irq_restore(flags);
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}
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void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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struct hstate *hstate = hstate_file(vma->vm_file);
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unsigned long tsize = huge_page_shift(hstate) - 10;
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__flush_tlb_page(vma->vm_mm, vmaddr, tsize, 0);
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}
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