6fbde6b492
Current Loongson-3 code can share among all Loongson64 processors. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com
46 lines
979 B
C
46 lines
979 B
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009 Lemote Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*/
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#include <linux/memblock.h>
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#include <asm/bootinfo.h>
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#include <asm/traps.h>
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#include <asm/smp-ops.h>
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#include <asm/cacheflush.h>
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#include <loongson.h>
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static void __init mips_nmi_setup(void)
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{
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void *base;
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extern char except_vec_nmi;
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base = (void *)(CAC_BASE + 0x380);
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memcpy(base, &except_vec_nmi, 0x80);
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flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
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}
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void __init prom_init(void)
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{
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prom_init_cmdline();
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prom_init_env();
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/* init base address of io space */
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set_io_port_base((unsigned long)
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ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
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prom_init_numa_memory();
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/* Hardcode to CPU UART 0 */
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setup_8250_early_printk_port(TO_UNCAC(LOONGSON_REG_BASE + 0x1e0), 0, 1024);
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register_smp_ops(&loongson3_smp_ops);
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board_nmi_handler_setup = mips_nmi_setup;
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}
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void __init prom_free_prom_memory(void)
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{
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}
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