Files
android_kernel_xiaomi_sm8450/drivers/gpu/drm/fsl-dcu
Stefan Agner 6cc4758ae9 drm/fsl-dcu: fix endian issue when using clk_register_divider
Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.

Cc: stable@vger.kernel.org
Fixes: 2d701449bc ("drm/fsl-dcu: use common clock framework for pixel clock divider")
Reported-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Meng Yi <meng.yi@nxp.com>
2016-09-05 12:11:50 -07:00
..
2016-04-25 20:27:18 -07:00
2016-04-25 20:27:18 -07:00