Reza Amini 471c1dd954 drm/amd/display: Allow asic specific FSFT timing optimization ...

[Why]
Each asic can optimize best based on its capabilities

[How]
Optimizing timing for a new pixel clock

Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2020-08-06 16:40:18 -04:00

..

color

drm/amd/display: fix compilation error on allmodconfig

2020-07-01 01:59:24 -04:00

freesync

drm/amd/display: Allow asic specific FSFT timing optimization

2020-08-06 16:40:18 -04:00

hdcp

drm/amd/display: fix typo

2020-04-09 10:43:16 -04:00

inc

drm/amd/display: Fix incorrect rounding for 10Hz refresh range

2020-07-02 12:02:54 -04:00

info_packet

drm/amd/display: move location of dmub_srv.h file

2020-05-05 13:12:33 -04:00

power

drm/amd: add missing fill of the array`s first element

2020-07-01 01:59:21 -04:00

vmid

drm/amd/display: correct rn NUM_VMID

2020-05-21 12:48:43 -04:00