670310dfba
Pull irq core updates from Thomas Gleixner:
"A rather large update for the interrupt core code and the irq chip drivers:
- Add a new bitmap matrix allocator and supporting changes, which is
used to replace the x86 vector allocator which comes with separate
pull request. This allows to replace the convoluted nested loop
allocation function in x86 with a facility which supports the
recently added property of managed interrupts proper and allows to
switch to a best effort vector reservation scheme, which addresses
problems with vector exhaustion.
- A large update to the ARM GIC-V3-ITS driver adding support for
range selectors.
- New interrupt controllers:
- Meson and Meson8 GPIO
- BCM7271 L2
- Socionext EXIU
If you expected that this will stop at some point, I have to
disappoint you. There are new ones posted already. Sigh!
- STM32 interrupt controller support for new platforms.
- A pile of fixes, cleanups and updates to the MIPS GIC driver
- The usual small fixes, cleanups and updates all over the place.
Most visible one is to move the irq chip drivers Kconfig switches
into a separate Kconfig menu"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits)
genirq: Fix type of shifting literal 1 in __setup_irq()
irqdomain: Drop pointless NULL check in virq_debug_show_one
genirq/proc: Return proper error code when irq_set_affinity() fails
irq/work: Use llist_for_each_entry_safe
irqchip: mips-gic: Print warning if inherited GIC base is used
irqchip/mips-gic: Add pr_fmt and reword pr_* messages
irqchip/stm32: Move the wakeup on interrupt mask
irqchip/stm32: Fix initial values
irqchip/stm32: Add stm32h7 support
dt-bindings/interrupt-controllers: Add compatible string for stm32h7
irqchip/stm32: Add multi-bank management
irqchip/stm32: Select GENERIC_IRQ_CHIP
irqchip/exiu: Add support for Socionext Synquacer EXIU controller
dt-bindings: Add description of Socionext EXIU interrupt controller
irqchip/gic-v3-its: Fix VPE activate callback return value
irqchip: mips-gic: Make IPI bitmaps static
irqchip: mips-gic: Share register writes in gic_set_type()
irqchip: mips-gic: Remove gic_vpes variable
irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs
irqchip: mips-gic: Configure EIC when CPUs come online
...
65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_IRQDOMAIN_H
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#define _ASM_IRQDOMAIN_H
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#include <linux/irqdomain.h>
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#include <asm/hw_irq.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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enum {
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/* Allocate contiguous CPU vectors */
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X86_IRQ_ALLOC_CONTIGUOUS_VECTORS = 0x1,
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};
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extern struct irq_domain *x86_vector_domain;
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extern void init_irq_alloc_info(struct irq_alloc_info *info,
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const struct cpumask *mask);
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extern void copy_irq_alloc_info(struct irq_alloc_info *dst,
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struct irq_alloc_info *src);
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#endif /* CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_X86_IO_APIC
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struct device_node;
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struct irq_data;
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enum ioapic_domain_type {
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IOAPIC_DOMAIN_INVALID,
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IOAPIC_DOMAIN_LEGACY,
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IOAPIC_DOMAIN_STRICT,
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IOAPIC_DOMAIN_DYNAMIC,
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};
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struct ioapic_domain_cfg {
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enum ioapic_domain_type type;
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const struct irq_domain_ops *ops;
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struct device_node *dev;
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};
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extern const struct irq_domain_ops mp_ioapic_irqdomain_ops;
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extern int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg);
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extern void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs);
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extern int mp_irqdomain_activate(struct irq_domain *domain,
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struct irq_data *irq_data, bool early);
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extern void mp_irqdomain_deactivate(struct irq_domain *domain,
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struct irq_data *irq_data);
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extern int mp_irqdomain_ioapic_idx(struct irq_domain *domain);
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#endif /* CONFIG_X86_IO_APIC */
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#ifdef CONFIG_PCI_MSI
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extern void arch_init_msi_domain(struct irq_domain *domain);
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#else
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static inline void arch_init_msi_domain(struct irq_domain *domain) { }
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#endif
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#ifdef CONFIG_HT_IRQ
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extern void arch_init_htirq_domain(struct irq_domain *domain);
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#else
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static inline void arch_init_htirq_domain(struct irq_domain *domain) { }
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#endif
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#endif
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