Files
android_kernel_xiaomi_sm8450/drivers/net/ethernet/qlogic/qed
Tomer Tayar 60afed72f5 qed: Configure cacheline size in HW
Default HW configuration is optimal for an architecture where cache
line size is 64B.

During chip initialization, properly initialize the cache line size
in HW to avoid possible redundant PCI transactions.

Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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