Ard Biesheuvel 558b01654d
irqchip/gic-v3: Add workaround for Synquacer pre-ITS ...
The Socionext Synquacer SoC's implementation of GICv3 has a so-called
'pre-ITS', which maps 32-bit writes targeted at a separate window of
size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device
ID taken from bits [device_id_bits + 1:2] of the window offset.
Writes that target GITS_TRANSLATER directly are reported as originating
from device ID #0 .
So add a workaround for this. Given that this breaks isolation, clear
the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well.
Acked-by: Rob Herring <robh@kernel.org >
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org >
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com >
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