5513c760db
Most IO block offsets have changed in XLP9XX. Update iomap.h to add the new addresses of different SoC blocks like PIC, SYS, UART etc. that are needed by the base code. On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus corresponding to the node. Update iomap code to reflect this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6277/
324 lines
8.6 KiB
C
324 lines
8.6 KiB
C
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/bridge.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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/* Main initialization */
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void nlm_node_init(int node)
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{
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struct nlm_soc_info *nodep;
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nodep = nlm_get_node(node);
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nodep->sysbase = nlm_get_sys_regbase(node);
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nodep->picbase = nlm_get_pic_regbase(node);
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nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
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if (cpu_is_xlp9xx())
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nodep->socbus = xlp9xx_get_socbus(node);
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else
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nodep->socbus = 0;
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spin_lock_init(&nodep->piclock);
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}
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int nlm_irq_to_irt(int irq)
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{
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uint64_t pcibase;
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int devoff, irt;
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devoff = 0;
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switch (irq) {
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case PIC_UART_0_IRQ:
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devoff = XLP_IO_UART0_OFFSET(0);
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break;
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case PIC_UART_1_IRQ:
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devoff = XLP_IO_UART1_OFFSET(0);
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break;
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case PIC_MMC_IRQ:
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devoff = XLP_IO_SD_OFFSET(0);
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break;
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case PIC_I2C_0_IRQ: /* I2C will be fixed up */
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case PIC_I2C_1_IRQ:
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case PIC_I2C_2_IRQ:
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case PIC_I2C_3_IRQ:
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if (cpu_is_xlpii())
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devoff = XLP2XX_IO_I2C_OFFSET(0);
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else
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devoff = XLP_IO_I2C0_OFFSET(0);
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break;
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default:
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if (cpu_is_xlpii()) {
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switch (irq) {
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/* XLP2XX has three XHCI USB controller */
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case PIC_2XX_XHCI_0_IRQ:
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devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
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break;
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case PIC_2XX_XHCI_1_IRQ:
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devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
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break;
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case PIC_2XX_XHCI_2_IRQ:
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devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
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break;
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}
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} else {
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switch (irq) {
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case PIC_EHCI_0_IRQ:
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devoff = XLP_IO_USB_EHCI0_OFFSET(0);
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break;
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case PIC_EHCI_1_IRQ:
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devoff = XLP_IO_USB_EHCI1_OFFSET(0);
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break;
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case PIC_OHCI_0_IRQ:
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devoff = XLP_IO_USB_OHCI0_OFFSET(0);
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break;
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case PIC_OHCI_1_IRQ:
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devoff = XLP_IO_USB_OHCI1_OFFSET(0);
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break;
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case PIC_OHCI_2_IRQ:
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devoff = XLP_IO_USB_OHCI2_OFFSET(0);
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break;
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case PIC_OHCI_3_IRQ:
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devoff = XLP_IO_USB_OHCI3_OFFSET(0);
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break;
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}
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}
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}
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if (devoff != 0) {
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pcibase = nlm_pcicfg_base(devoff);
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irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
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/* HW weirdness, I2C IRT entry has to be fixed up */
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switch (irq) {
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case PIC_I2C_1_IRQ:
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irt = irt + 1; break;
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case PIC_I2C_2_IRQ:
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irt = irt + 2; break;
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case PIC_I2C_3_IRQ:
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irt = irt + 3; break;
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}
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} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
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irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
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/* HW bug, PCI IRT entries are bad on early silicon, fix */
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irt = PIC_IRT_PCIE_LINK_INDEX(irq -
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PIC_PCIE_LINK_LEGACY_IRQ_BASE);
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} else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
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irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
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irt = -2;
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} else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
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irq <= PIC_PCIE_MSIX_IRQ(3)) {
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irt = -2;
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} else {
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irt = -1;
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}
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return irt;
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}
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unsigned int nlm_get_core_frequency(int node, int core)
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{
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unsigned int pll_divf, pll_divr, dfs_div, ext_div;
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unsigned int rstval, dfsval, denom;
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uint64_t num, sysbase;
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sysbase = nlm_get_node(node)->sysbase;
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rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
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if (cpu_is_xlpii()) {
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num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
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denom = 3;
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} else {
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dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
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pll_divf = ((rstval >> 10) & 0x7f) + 1;
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pll_divr = ((rstval >> 8) & 0x3) + 1;
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ext_div = ((rstval >> 30) & 0x3) + 1;
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dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
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num = 800000000ULL * pll_divf;
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denom = 3 * pll_divr * ext_div * dfs_div;
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}
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do_div(num, denom);
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return (unsigned int)num;
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}
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/* Calculate Frequency to the PIC from PLL.
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* freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
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* ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
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*/
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static unsigned int nlm_2xx_get_pic_frequency(int node)
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{
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u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
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u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
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u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
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sysbase = nlm_get_node(node)->sysbase;
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/* Find ref_clk_base */
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ref_clk_select =
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(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
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switch (ref_clk_select) {
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case 0:
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ref_clk = 200000000ULL;
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ref_div = 3;
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break;
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case 1:
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ref_clk = 100000000ULL;
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ref_div = 1;
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break;
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case 2:
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ref_clk = 125000000ULL;
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ref_div = 1;
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break;
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case 3:
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ref_clk = 400000000ULL;
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ref_div = 3;
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break;
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}
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/* Find the clock source PLL device for PIC */
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reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
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switch (reg_select) {
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case 0:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
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break;
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case 1:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
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break;
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case 2:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
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break;
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case 3:
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ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
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ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
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break;
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}
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vco_post_div = (ctrl_val0 >> 5) & 0x7;
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pll_post_div = (ctrl_val0 >> 24) & 0x7;
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mdiv = ctrl_val2 & 0xff;
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fdiv = (ctrl_val2 >> 8) & 0xfff;
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/* Find PLL post divider value */
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switch (pll_post_div) {
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case 1:
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pll_post_div = 2;
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break;
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case 3:
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pll_post_div = 4;
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break;
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case 7:
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pll_post_div = 8;
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break;
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case 6:
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pll_post_div = 16;
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break;
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case 0:
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default:
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pll_post_div = 1;
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break;
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}
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fdiv = fdiv/(1 << 13);
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pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
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pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
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if (pll_out_freq_den > 0)
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do_div(pll_out_freq_num, pll_out_freq_den);
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/* PIC post divider, which happens after PLL */
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pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
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do_div(pll_out_freq_num, 1 << pic_div);
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return pll_out_freq_num;
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}
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unsigned int nlm_get_pic_frequency(int node)
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{
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if (cpu_is_xlpii())
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return nlm_2xx_get_pic_frequency(node);
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else
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return 133333333;
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}
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unsigned int nlm_get_cpu_frequency(void)
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{
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return nlm_get_core_frequency(0, 0);
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}
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/*
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* Fills upto 8 pairs of entries containing the DRAM map of a node
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* if n < 0, get dram map for all nodes
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*/
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int xlp_get_dram_map(int n, uint64_t *dram_map)
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{
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uint64_t bridgebase, base, lim;
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uint32_t val;
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int i, node, rv;
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/* Look only at mapping on Node 0, we don't handle crazy configs */
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bridgebase = nlm_get_bridge_regbase(0);
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rv = 0;
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for (i = 0; i < 8; i++) {
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val = nlm_read_bridge_reg(bridgebase,
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BRIDGE_DRAM_NODE_TRANSLN(i));
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node = (val >> 1) & 0x3;
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if (n >= 0 && n != node)
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continue;
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val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
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val = (val >> 12) & 0xfffff;
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base = (uint64_t) val << 20;
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val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
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val = (val >> 12) & 0xfffff;
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if (val == 0) /* BAR not used */
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continue;
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lim = ((uint64_t)val + 1) << 20;
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dram_map[rv] = base;
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dram_map[rv + 1] = lim;
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rv += 2;
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}
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return rv;
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}
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