5317ce310c
Migrate MSM Adreno Governor TZ interface to upstream SCM driver. Change-Id: I1c4347d33b6be835f04422918c29e9c627e02874 Signed-off-by: Elliot Berman <eberman@codeaurora.org> Signed-off-by: Siddharth Gupta <sidgup@codeaurora.org>
184 lines
8.3 KiB
C
184 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*/
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#ifndef __QCOM_SCM_H
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#define __QCOM_SCM_H
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#include <linux/err.h>
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#include <linux/types.h>
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#include <linux/cpumask.h>
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#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
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#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
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#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
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struct qcom_scm_hdcp_req {
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u32 addr;
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u32 val;
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};
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struct qcom_scm_vmperm {
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int vmid;
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int perm;
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};
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#define QCOM_SCM_VMID_HLOS 0x3
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#define QCOM_SCM_VMID_MSS_MSA 0xF
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#define QCOM_SCM_VMID_WLAN 0x18
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#define QCOM_SCM_VMID_WLAN_CE 0x19
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#define QCOM_SCM_PERM_READ 0x4
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#define QCOM_SCM_PERM_WRITE 0x2
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#define QCOM_SCM_PERM_EXEC 0x1
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#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
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#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
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#if IS_ENABLED(CONFIG_QCOM_SCM)
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extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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extern void qcom_scm_cpu_power_down(u32 flags);
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extern int qcom_scm_sec_wdog_deactivate(void);
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size);
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size);
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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extern int qcom_scm_get_sec_dump_state(u32 *dump_state);
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extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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extern int qcom_scm_io_reset(void);
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extern int qcom_scm_get_jtag_etm_feat_id(u64 *version);
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extern void qcom_scm_mmu_sync(bool sync);
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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extern int qcom_scm_mem_protect_region_id(phys_addr_t paddr, size_t size);
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extern int qcom_scm_mem_protect_lock_id2_flat(phys_addr_t list_addr,
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size_t list_size, size_t chunk_size,
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size_t memory_usage, int lock);
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extern int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr, size_t num_sg,
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size_t sg_block_size, u64 sec_id, int cbndx,
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unsigned long iova, size_t total_len);
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extern int qcom_scm_iommu_secure_unmap(u64 sec_id, int cbndx,
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unsigned long iova, size_t total_len);
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extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt);
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extern bool qcom_scm_kgsl_set_smmu_aperture_available(void);
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extern int qcom_scm_kgsl_set_smmu_aperture(
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unsigned int num_context_bank);
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extern int qcom_scm_smmu_prepare_atos_id(u64 dev_id, int cb_num, int operation);
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extern bool qcom_scm_dcvs_core_available(void);
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extern bool qcom_scm_dcvs_ca_available(void);
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extern int qcom_scm_dcvs_reset(void);
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extern int qcom_scm_dcvs_init_v2(phys_addr_t addr, size_t size, int *version);
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extern int qcom_scm_dcvs_init_ca_v2(phys_addr_t addr, size_t size);
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extern int qcom_scm_dcvs_update(int level, s64 total_time, s64 busy_time);
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extern int qcom_scm_dcvs_update_v2(int level, s64 total_time, s64 busy_time);
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extern int qcom_scm_dcvs_update_ca_v2(int level, s64 total_time, s64 busy_time,
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int context_count);
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp);
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extern int qcom_scm_enable_shm_bridge(void);
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extern int qcom_scm_delete_shm_bridge(u64 handle);
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extern int qcom_scm_create_shm_bridge(u64 pfn_and_ns_perm_flags,
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u64 ipfn_and_s_perm_flags, u64 size_and_flags,
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u64 ns_vmids, u64 *handle);
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extern int qcom_scm_smmu_change_pgtbl_format(u64 dev_id, int cbndx);
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extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
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extern int qcom_scm_ice_restore_cfg(void);
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extern bool qcom_scm_is_available(void);
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#else
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#include <linux/errno.h>
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static inline
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{ return -ENODEV; }
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static inline
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{ return -ENODEV; }
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static inline void qcom_scm_cpu_power_down(u32 flags) {}
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static inline int qcom_scm_sec_wdog_deactivate(void) { return -ENODEV; }
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static inline u32 qcom_scm_set_remote_state(u32 state, u32 id)
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{ return -ENODEV; }
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static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size) { return -ENODEV; }
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static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size) { return -ENODEV; }
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static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
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{ return -ENODEV; }
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static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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static inline int qcom_scm_get_sec_dump_state(u32 *dump_state)
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{return -ENODEV; }
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static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
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{ return -ENODEV; }
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static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
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{ return -ENODEV; }
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static inline int qcom_scm_io_reset(void)
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{ return -ENODEV; }
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static inline int qcom_scm_get_jtag_etm_feat_id(u64 *version)
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{ return -ENODEV; }
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static inline void qcom_scm_mmu_sync(bool sync) {}
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static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
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{ return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
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{ return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
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{ return -ENODEV; }
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static inline int qcom_scm_mem_protect_region_id(phys_addr_t paddr, size_t size)
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{ return -ENODEV; }
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static inline int qcom_scm_mem_protect_lock_id2_flat(phys_addr_t list_addr,
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size_t list_size, size_t chunk_size, size_t memory_usage,
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int lock) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr,
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size_t num_sg, size_t sg_block_size, u64 sec_id, int cbndx,
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unsigned long iova, size_t total_len) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_unmap(u64 sec_id, int cbndx,
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unsigned long iova, size_t total_len) { return -ENODEV; }
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static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt) { return -ENODEV; }
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static inline bool qcom_scm_kgsl_set_smmu_aperture_available(void)
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{ return false; }
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static inline int qcom_scm_kgsl_set_smmu_aperture(
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unsigned int num_context_bank) { return -ENODEV; }
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static inline int qcom_scm_smmu_prepare_atos_id(u64 dev_id, int cb_num,
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int operation) { return -ENODEV; }
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static inline bool qcom_scm_dcvs_core_available(void) { return false; }
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static inline bool qcom_scm_dcvs_ca_available(void) { return false; }
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static inline int qcom_scm_dcvs_init_v2(phys_addr_t addr, size_t size,
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int *version) { return -ENODEV; }
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static inline int qcom_scm_dcvs_init_ca_v2(phys_addr_t addr, size_t size)
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{ return -ENODEV; }
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static inline int qcom_scm_dcvs_update(int level, s64 total_time, s64 busy_time)
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{ return -ENODEV; }
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static inline int qcom_scm_dcvs_update_v2(int level, s64 total_time,
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s64 busy_time) { return -ENODEV; }
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static inline int qcom_scm_dcvs_update_ca_v2(int level, s64 total_time,
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s64 busy_time, int context_count) { return -ENODEV; }
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static inline bool qcom_scm_hdcp_available(void) { return false; }
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static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp) { return -ENODEV; }
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static inline int qcom_scm_enable_shm_bridge(void) { return -ENODEV; }
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static inline int qcom_scm_delete_shm_bridge(u64 handle) { return -ENODEV; }
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static inline int qcom_scm_create_shm_bridge(u64 pfn_and_ns_perm_flags,
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u64 ipfn_and_s_perm_flags, u64 size_and_flags,
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u64 ns_vmids, u64 *handle) { return -ENODEV; }
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static inline int qcom_scm_smmu_change_pgtbl_format(u64 dev_id, int cbndx)
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{ return -ENODEV; }
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static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
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{ return -ENODEV; }
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static inline int qcom_scm_ice_restore_cfg(void) { return -ENODEV; }
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static inline bool qcom_scm_is_available(void) { return false; }
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#endif
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#endif
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