c6778ff813
Pull ARM 64-bit DT updates from Olof Johansson:
"Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
of smaller changes, but also some new platforms that are worth
mentioning:
- Rockchip RK3399 platforms for Chromebooks, including Samsung
Chromebook Plus (Kevin)
- Orange Pi PC2 (Allwinner H5)
- Freescale LS2088A and LS1088A SoCs
- Expanded support for Nvidia Tegra186 (and Jetson TX2)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
...
47 lines
1.0 KiB
C
47 lines
1.0 KiB
C
/*
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* GXBB clock tree IDs
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*/
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#ifndef __GXBB_CLKC_H
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#define __GXBB_CLKC_H
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#define CLKID_CPUCLK 1
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#define CLKID_HDMI_PLL 2
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL2 15
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_AIU_GLUE 38
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#define CLKID_I2S_OUT 40
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#define CLKID_MIXER_IFACE 44
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#define CLKID_AIU 47
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_SANA 69
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_AOCLK_GATE 80
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#define CLKID_AO_I2C 93
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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#define CLKID_SD_EMMC_C 96
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#define CLKID_SAR_ADC_CLK 97
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#define CLKID_SAR_ADC_SEL 98
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#define CLKID_MALI_0_SEL 100
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#define CLKID_MALI_0 102
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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#endif /* __GXBB_CLKC_H */
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