4e0e161d3c
Having to call qe_ic_init() from platform-specific code makes it awkward to allow building the QE drivers for ARM. It's also a needless duplication of code, and slightly error-prone: Instead of the caller needing to know the details of whether the QUICC Engine High and QUICC Engine Low are actually the same interrupt (see e.g. the machine_is() in mpc85xx_mds_qeic_init), just let the init function choose the appropriate handlers after it has parsed the DT and figured it out. If the two interrupts are distinct, use separate handlers, otherwise use the handler which first checks the CHIVEC register (for the high priority interrupts), then the CIVEC. All existing callers pass 0 for flags, so continue to do that from the new single caller. Later cleanups will remove that argument from qe_ic_init and simplify the body, as well as make qe_ic_init into a proper init function for an IRQCHIP_DECLARE, eliminating the need to manually look up the fsl,qe-ic node. Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
161 lines
3.3 KiB
C
161 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* misc setup functions for MPC83xx
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*
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <asm/debug.h>
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#include <asm/io.h>
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#include <asm/hw_irq.h>
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#include <asm/ipic.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <mm/mmu_decl.h>
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#include "mpc83xx.h"
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static __be32 __iomem *restart_reg_base;
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static int __init mpc83xx_restart_init(void)
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{
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/* map reset restart_reg_baseister space */
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restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
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return 0;
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}
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arch_initcall(mpc83xx_restart_init);
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void __noreturn mpc83xx_restart(char *cmd)
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{
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#define RST_OFFSET 0x00000900
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#define RST_PROT_REG 0x00000018
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#define RST_CTRL_REG 0x0000001c
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local_irq_disable();
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if (restart_reg_base) {
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/* enable software reset "RSTE" */
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out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
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/* set software hard reset */
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out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
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} else {
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printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
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}
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for (;;) ;
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}
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long __init mpc83xx_time_init(void)
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{
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#define SPCR_OFFSET 0x00000110
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#define SPCR_TBEN 0x00400000
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__be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
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__be32 tmp;
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tmp = in_be32(spcr);
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out_be32(spcr, tmp | SPCR_TBEN);
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iounmap(spcr);
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return 0;
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}
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void __init mpc83xx_ipic_init_IRQ(void)
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{
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struct device_node *np;
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/* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
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np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
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if (!np)
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np = of_find_node_by_type(NULL, "ipic");
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if (!np)
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return;
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ipic_init(np, 0);
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of_node_put(np);
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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ipic_set_default_priority();
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}
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#ifdef CONFIG_QUICC_ENGINE
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void __init mpc83xx_ipic_and_qe_init_IRQ(void)
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{
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mpc83xx_ipic_init_IRQ();
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}
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#endif /* CONFIG_QUICC_ENGINE */
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static const struct of_device_id of_bus_ids[] __initconst = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .compatible = "simple-bus" },
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{ .compatible = "gianfar" },
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{ .compatible = "gpio-leds", },
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{ .type = "qe", },
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{ .compatible = "fsl,qe", },
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{},
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};
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int __init mpc83xx_declare_of_platform_devices(void)
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{
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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return 0;
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}
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#ifdef CONFIG_PCI
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void __init mpc83xx_setup_pci(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
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mpc83xx_add_bridge(np);
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for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
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mpc83xx_add_bridge(np);
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}
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#endif
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void __init mpc83xx_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("mpc83xx_setup_arch()", 0);
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if (!__map_without_bats) {
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phys_addr_t immrbase = get_immrbase();
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int immrsize = IS_ALIGNED(immrbase, SZ_2M) ? SZ_2M : SZ_1M;
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unsigned long va = fix_to_virt(FIX_IMMR_BASE);
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setbat(-1, va, immrbase, immrsize, PAGE_KERNEL_NCG);
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update_bats();
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}
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mpc83xx_setup_pci();
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}
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int machine_check_83xx(struct pt_regs *regs)
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{
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u32 mask = 1 << (31 - IPIC_MCP_WDT);
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if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
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return machine_check_generic(regs);
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ipic_clear_mcp_status(mask);
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if (debugger_fault_handler(regs))
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return 1;
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die("Watchdog NMI Reset", regs, 0);
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return 1;
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}
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