c2c59456e1
In previous discussion [1] and [2], we found that it is risky to use max_pfn or totalram_pages to tell if 4GB mode is enabled. Check 4GB mode by reading infracfg register, remove the usage of the un-exported symbol max_pfn. This is a step towards building mtk_iommu as a kernel module. [1] https://lore.kernel.org/lkml/20200603161132.2441-1-miles.chen@mediatek.com/ [2] https://lore.kernel.org/lkml/20200604080120.2628-1-miles.chen@mediatek.com/ [3] https://lore.kernel.org/lkml/20200715205120.GA778876@bogus/ Cc: Mike Rapoport <rppt@linux.ibm.com> Cc: David Hildenbrand <david@redhat.com> Cc: Yong Wu <yong.wu@mediatek.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Rob Herring <robh@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Joerg Roedel <joro@8bytes.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20200904104038.4979-1-miles.chen@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
43 lines
1.6 KiB
C
43 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SOC_MEDIATEK_INFRACFG_H
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#define __SOC_MEDIATEK_INFRACFG_H
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#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
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#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
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#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
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#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
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#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
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#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
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#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
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#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
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#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
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#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
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#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
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#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
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#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
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#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
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#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
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#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
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#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
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#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
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#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
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#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
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#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
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#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
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#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
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#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
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BIT(28))
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#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
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BIT(7) | BIT(8))
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#define REG_INFRA_MISC 0xf00
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#define F_DDR_4GB_SUPPORT_EN BIT(13)
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int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
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bool reg_update);
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int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
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bool reg_update);
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#endif /* __SOC_MEDIATEK_INFRACFG_H */
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