e012f9d1af
[ Upstream commit 0dcad700bb2776e3886fe0a645a4bf13b1e747cd ]
When scheduling a group of events, there are constraint checks done to
make sure all events can go in a group. Example, one of the criteria is
that events in a group cannot use the same PMC. But platform specific
PMU supports alternative event for some of the event codes. During
perf_event_open(), if any event group doesn't match constraint check
criteria, further lookup is done to find alternative event.
By current design, the array of alternatives events in PMU code is
expected to be sorted by column 0. This is because in
find_alternative() the return criteria is based on event code
comparison. ie. "event < ev_alt[i][0])". This optimisation is there
since find_alternative() can be called multiple times. In power9 PMU
code, the alternative event array is not sorted properly and hence there
is breakage in finding alternative events.
To work with existing logic, fix the alternative event array to be
sorted by column 0 for power9-pmu.c
Results:
With alternative events, multiplexing can be avoided. That is, for
example, in power9 PM_LD_MISS_L1 (0x3e054) has alternative event,
PM_LD_MISS_L1_ALT (0x400f0). This is an identical event which can be
programmed in a different PMC.
Before:
# perf stat -e r3e054,r300fc
Performance counter stats for 'system wide':
1057860 r3e054 (50.21%)
379 r300fc (49.79%)
0.944329741 seconds time elapsed
Since both the events are using PMC3 in this case, they are
multiplexed here.
After:
# perf stat -e r3e054,r300fc
Performance counter stats for 'system wide':
1006948 r3e054
182 r300fc
Fixes: 91e0bd1e62 ("powerpc/perf: Add PM_LD_MISS_L1 and PM_BR_2PATH to power9 event list")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220419114828.89843-1-atrajeev@linux.vnet.ibm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
475 lines
13 KiB
C
475 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Performance counter support for POWER9 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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*/
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#define pr_fmt(fmt) "power9-pmu: " fmt
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#include "isa207-common.h"
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/*
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* Raw event encoding for Power9:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
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* | | | | |
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* | | *- IFM (Linux) | thresh start/stop -*
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* | *- BHRB (Linux) *sm
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* *- EBB (Linux)
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ]
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* | | | | |
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* | | | | *- mark
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* | | *- L1/L2/L3 cache_sel |
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* | | |
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* | *- sampling mode for marked events *- combine
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* |
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* *- thresh_sel
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*
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* Below uses IBM bit numbering.
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*
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* MMCR1[x:y] = unit (PMCxUNIT)
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* MMCR1[24] = pmc1combine[0]
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* MMCR1[25] = pmc1combine[1]
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* MMCR1[26] = pmc2combine[0]
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* MMCR1[27] = pmc2combine[1]
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* MMCR1[28] = pmc3combine[0]
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* MMCR1[29] = pmc3combine[1]
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* MMCR1[30] = pmc4combine[0]
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* MMCR1[31] = pmc4combine[1]
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*
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* if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
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* MMCR1[20:27] = thresh_ctl
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* else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
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* MMCR1[20:27] = thresh_ctl
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* else
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* MMCRA[48:55] = thresh_ctl (THRESH START/END)
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*
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* if thresh_sel:
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* MMCRA[45:47] = thresh_sel
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*
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* if thresh_cmp:
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* MMCRA[9:11] = thresh_cmp[0:2]
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* MMCRA[12:18] = thresh_cmp[3:9]
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*
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* MMCR1[16] = cache_sel[2]
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* MMCR1[17] = cache_sel[3]
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*
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* if mark:
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* MMCRA[63] = 1 (SAMPLE_ENABLE)
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* MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
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* MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
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*
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* if EBB and BHRB:
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* MMCRA[32:33] = IFM
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*
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* MMCRA[SDAR_MODE] = sm
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*/
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/*
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* Some power9 event codes.
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*/
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#define EVENT(_name, _code) _name = _code,
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enum {
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#include "power9-events-list.h"
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};
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#undef EVENT
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/* MMCRA IFM bits - POWER9 */
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#define POWER9_MMCRA_IFM1 0x0000000040000000UL
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#define POWER9_MMCRA_IFM2 0x0000000080000000UL
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#define POWER9_MMCRA_IFM3 0x00000000C0000000UL
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#define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL
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extern u64 PERF_REG_EXTENDED_MASK;
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/* Nasty Power9 specific hack */
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#define PVR_POWER9_CUMULUS 0x00002000
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/* PowerISA v2.07 format attribute structure*/
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extern struct attribute_group isa207_pmu_format_group;
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int p9_dd21_bl_ev[] = {
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PM_MRK_ST_DONE_L2,
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PM_RADIX_PWC_L1_HIT,
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PM_FLOP_CMPL,
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PM_MRK_NTF_FIN,
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PM_RADIX_PWC_L2_HIT,
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PM_IFETCH_THROTTLE,
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PM_MRK_L2_TM_ST_ABORT_SISTER,
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PM_RADIX_PWC_L3_HIT,
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PM_RUN_CYC_SMT2_MODE,
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PM_TM_TX_PASS_RUN_INST,
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PM_DISP_HELD_SYNC_HOLD,
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};
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int p9_dd22_bl_ev[] = {
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PM_DTLB_MISS_16G,
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PM_DERAT_MISS_2M,
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PM_DTLB_MISS_2M,
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PM_MRK_DTLB_MISS_1G,
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PM_DTLB_MISS_4K,
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PM_DERAT_MISS_1G,
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PM_MRK_DERAT_MISS_2M,
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PM_MRK_DTLB_MISS_4K,
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PM_MRK_DTLB_MISS_16G,
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PM_DTLB_MISS_64K,
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PM_MRK_DERAT_MISS_1G,
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PM_MRK_DTLB_MISS_64K,
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PM_DISP_HELD_SYNC_HOLD,
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PM_DTLB_MISS_16M,
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PM_DTLB_MISS_1G,
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PM_MRK_DTLB_MISS_16M,
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};
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/* Table of alternatives, sorted by column 0 */
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static const unsigned int power9_event_alternatives[][MAX_ALT] = {
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{ PM_BR_2PATH, PM_BR_2PATH_ALT },
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{ PM_INST_DISP, PM_INST_DISP_ALT },
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{ PM_RUN_CYC_ALT, PM_RUN_CYC },
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{ PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
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{ PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
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};
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static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int num_alt = 0;
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num_alt = isa207_get_alternatives(event, alt,
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ARRAY_SIZE(power9_event_alternatives), flags,
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power9_event_alternatives);
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return num_alt;
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}
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GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
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GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
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GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
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GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
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GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
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GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
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GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
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CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
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CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
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CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
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CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
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CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
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CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
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CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
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CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
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CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
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CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
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CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
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CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
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CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
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static struct attribute *power9_events_attr[] = {
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GENERIC_EVENT_PTR(PM_CYC),
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GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
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GENERIC_EVENT_PTR(PM_CMPLU_STALL),
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GENERIC_EVENT_PTR(PM_INST_CMPL),
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GENERIC_EVENT_PTR(PM_BR_CMPL),
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GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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GENERIC_EVENT_PTR(PM_LD_REF_L1),
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GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
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GENERIC_EVENT_PTR(MEM_LOADS),
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GENERIC_EVENT_PTR(MEM_STORES),
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CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
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CACHE_EVENT_PTR(PM_LD_REF_L1),
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CACHE_EVENT_PTR(PM_L1_PREF),
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CACHE_EVENT_PTR(PM_ST_MISS_L1),
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CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
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CACHE_EVENT_PTR(PM_INST_FROM_L1),
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CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3),
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CACHE_EVENT_PTR(PM_L3_PREF_ALL),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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CACHE_EVENT_PTR(PM_BR_CMPL),
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CACHE_EVENT_PTR(PM_DTLB_MISS),
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CACHE_EVENT_PTR(PM_ITLB_MISS),
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NULL
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};
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static struct attribute_group power9_pmu_events_group = {
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.name = "events",
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.attrs = power9_events_attr,
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};
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PMU_FORMAT_ATTR(event, "config:0-51");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(mark, "config:8");
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PMU_FORMAT_ATTR(combine, "config:10-11");
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PMU_FORMAT_ATTR(unit, "config:12-15");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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PMU_FORMAT_ATTR(cache_sel, "config:20-23");
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PMU_FORMAT_ATTR(sample_mode, "config:24-28");
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PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
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PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
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PMU_FORMAT_ATTR(thresh_start, "config:36-39");
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PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
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PMU_FORMAT_ATTR(sdar_mode, "config:50-51");
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static struct attribute *power9_pmu_format_attr[] = {
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&format_attr_event.attr,
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&format_attr_pmcxsel.attr,
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&format_attr_mark.attr,
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&format_attr_combine.attr,
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&format_attr_unit.attr,
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&format_attr_pmc.attr,
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&format_attr_cache_sel.attr,
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&format_attr_sample_mode.attr,
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&format_attr_thresh_sel.attr,
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&format_attr_thresh_stop.attr,
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&format_attr_thresh_start.attr,
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&format_attr_thresh_cmp.attr,
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&format_attr_sdar_mode.attr,
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NULL,
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};
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static struct attribute_group power9_pmu_format_group = {
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.name = "format",
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.attrs = power9_pmu_format_attr,
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};
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static const struct attribute_group *power9_pmu_attr_groups[] = {
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&power9_pmu_format_group,
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&power9_pmu_events_group,
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NULL,
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};
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static int power9_generic_events[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
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[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
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[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
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[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
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[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
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};
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static u64 power9_bhrb_filter_map(u64 branch_sample_type)
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{
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u64 pmu_bhrb_filter = 0;
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/* BHRB and regular PMU events share the same privilege state
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* filter configuration. BHRB is always recorded along with a
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* regular PMU event. As the privilege state filter is handled
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* in the basic PMC configuration of the accompanying regular
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* PMU event, we ignore any separate BHRB specific request.
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*/
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/* No branch filter requested */
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if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
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return pmu_bhrb_filter;
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/* Invalid branch filter options - HW does not support */
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if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
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return -1;
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if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
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return -1;
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if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
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return -1;
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if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
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pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
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return pmu_bhrb_filter;
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}
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/* Every thing else is unsupported */
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return -1;
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}
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static void power9_config_bhrb(u64 pmu_bhrb_filter)
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{
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pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
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/* Enable BHRB filter in PMU */
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mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
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}
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
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[ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_ST_MISS_L1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = PM_L1_PREF,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(L1I) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
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[ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(LL) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
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[ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_DTLB_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_ITLB_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_BR_CMPL,
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[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
|
||
[ C(RESULT_ACCESS) ] = -1,
|
||
[ C(RESULT_MISS) ] = -1,
|
||
},
|
||
},
|
||
[ C(NODE) ] = {
|
||
[ C(OP_READ) ] = {
|
||
[ C(RESULT_ACCESS) ] = -1,
|
||
[ C(RESULT_MISS) ] = -1,
|
||
},
|
||
[ C(OP_WRITE) ] = {
|
||
[ C(RESULT_ACCESS) ] = -1,
|
||
[ C(RESULT_MISS) ] = -1,
|
||
},
|
||
[ C(OP_PREFETCH) ] = {
|
||
[ C(RESULT_ACCESS) ] = -1,
|
||
[ C(RESULT_MISS) ] = -1,
|
||
},
|
||
},
|
||
};
|
||
|
||
#undef C
|
||
|
||
static struct power_pmu power9_pmu = {
|
||
.name = "POWER9",
|
||
.n_counter = MAX_PMU_COUNTERS,
|
||
.add_fields = ISA207_ADD_FIELDS,
|
||
.test_adder = ISA207_TEST_ADDER,
|
||
.group_constraint_mask = CNST_CACHE_PMC4_MASK,
|
||
.group_constraint_val = CNST_CACHE_PMC4_VAL,
|
||
.compute_mmcr = isa207_compute_mmcr,
|
||
.config_bhrb = power9_config_bhrb,
|
||
.bhrb_filter_map = power9_bhrb_filter_map,
|
||
.get_constraint = isa207_get_constraint,
|
||
.get_alternatives = power9_get_alternatives,
|
||
.get_mem_data_src = isa207_get_mem_data_src,
|
||
.get_mem_weight = isa207_get_mem_weight,
|
||
.disable_pmc = isa207_disable_pmc,
|
||
.flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
|
||
.n_generic = ARRAY_SIZE(power9_generic_events),
|
||
.generic_events = power9_generic_events,
|
||
.cache_events = &power9_cache_events,
|
||
.attr_groups = power9_pmu_attr_groups,
|
||
.bhrb_nr = 32,
|
||
.capabilities = PERF_PMU_CAP_EXTENDED_REGS,
|
||
};
|
||
|
||
int init_power9_pmu(void)
|
||
{
|
||
int rc = 0;
|
||
unsigned int pvr = mfspr(SPRN_PVR);
|
||
|
||
/* Comes from cpu_specs[] */
|
||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
|
||
return -ENODEV;
|
||
|
||
/* Blacklist events */
|
||
if (!(pvr & PVR_POWER9_CUMULUS)) {
|
||
if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) {
|
||
power9_pmu.blacklist_ev = p9_dd21_bl_ev;
|
||
power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev);
|
||
} else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) {
|
||
power9_pmu.blacklist_ev = p9_dd22_bl_ev;
|
||
power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev);
|
||
}
|
||
}
|
||
|
||
/* Set the PERF_REG_EXTENDED_MASK here */
|
||
PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_300;
|
||
|
||
rc = register_power_pmu(&power9_pmu);
|
||
if (rc)
|
||
return rc;
|
||
|
||
/* Tell userspace that EBB is supported */
|
||
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
|
||
|
||
return 0;
|
||
}
|