406f992e4a
On Intel hardware, native_play_dead() uses mwait_play_dead() by default and only falls back to the other methods if that fails. That also happens during resume from hibernation, when the restore (boot) kernel runs disable_nonboot_cpus() to take all of the CPUs except for the boot one offline. However, that is problematic, because the address passed to __monitor() in mwait_play_dead() is likely to be written to in the last phase of hibernate image restoration and that causes the "dead" CPU to start executing instructions again. Unfortunately, the page containing the address in that CPU's instruction pointer may not be valid any more at that point. First, that page may have been overwritten with image kernel memory contents already, so the instructions the CPU attempts to execute may simply be invalid. Second, the page tables previously used by that CPU may have been overwritten by image kernel memory contents, so the address in its instruction pointer is impossible to resolve then. A report from Varun Koyyalagunta and investigation carried out by Chen Yu show that the latter sometimes happens in practice. To prevent it from happening, temporarily change the smp_ops.play_dead pointer during resume from hibernation so that it points to a special "play dead" routine which uses hlt_play_dead() and avoids the inadvertent "revivals" of "dead" CPUs this way. A slightly unpleasant consequence of this change is that if the system is hibernated with one or more CPUs offline, it will generally draw more power after resume than it did before hibernation, because the physical state entered by CPUs via hlt_play_dead() is higher-power than the mwait_play_dead() one in the majority of cases. It is possible to work around this, but it is unclear how much of a problem that's going to be in practice, so the workaround will be implemented later if it turns out to be necessary. Link: https://bugzilla.kernel.org/show_bug.cgi?id=106371 Reported-by: Varun Koyyalagunta <cpudebug@centtech.com> Original-by: Chen Yu <yu.c.chen@intel.com> Tested-by: Chen Yu <yu.c.chen@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Ingo Molnar <mingo@kernel.org>
215 lines
5.1 KiB
C
215 lines
5.1 KiB
C
#ifndef _ASM_X86_SMP_H
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#define _ASM_X86_SMP_H
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#ifndef __ASSEMBLY__
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#include <linux/cpumask.h>
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#include <asm/percpu.h>
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/*
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* We need the APIC definitions automatically as part of 'smp.h'
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*/
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#ifdef CONFIG_X86_LOCAL_APIC
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# include <asm/mpspec.h>
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# include <asm/apic.h>
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# ifdef CONFIG_X86_IO_APIC
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# include <asm/io_apic.h>
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# endif
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#endif
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#include <asm/thread_info.h>
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#include <asm/cpumask.h>
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extern int smp_num_siblings;
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extern unsigned int num_processors;
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DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
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DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
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/* cpus sharing the last level cache: */
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DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
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DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id);
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DECLARE_PER_CPU_READ_MOSTLY(int, cpu_number);
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static inline struct cpumask *cpu_llc_shared_mask(int cpu)
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{
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return per_cpu(cpu_llc_shared_map, cpu);
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}
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DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid);
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DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
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DECLARE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid);
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#endif
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/* Static state in head.S used to set up a CPU */
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extern unsigned long stack_start; /* Initial stack pointer address */
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struct task_struct;
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struct smp_ops {
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void (*smp_prepare_boot_cpu)(void);
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void (*smp_prepare_cpus)(unsigned max_cpus);
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void (*smp_cpus_done)(unsigned max_cpus);
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void (*stop_other_cpus)(int wait);
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void (*smp_send_reschedule)(int cpu);
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int (*cpu_up)(unsigned cpu, struct task_struct *tidle);
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int (*cpu_disable)(void);
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void (*cpu_die)(unsigned int cpu);
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void (*play_dead)(void);
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void (*send_call_func_ipi)(const struct cpumask *mask);
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void (*send_call_func_single_ipi)(int cpu);
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};
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/* Globals due to paravirt */
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extern void set_cpu_sibling_map(int cpu);
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#ifdef CONFIG_SMP
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extern struct smp_ops smp_ops;
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static inline void smp_send_stop(void)
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{
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smp_ops.stop_other_cpus(0);
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}
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static inline void stop_other_cpus(void)
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{
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smp_ops.stop_other_cpus(1);
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}
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static inline void smp_prepare_boot_cpu(void)
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{
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smp_ops.smp_prepare_boot_cpu();
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}
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static inline void smp_prepare_cpus(unsigned int max_cpus)
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{
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smp_ops.smp_prepare_cpus(max_cpus);
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}
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static inline void smp_cpus_done(unsigned int max_cpus)
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{
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smp_ops.smp_cpus_done(max_cpus);
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}
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static inline int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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return smp_ops.cpu_up(cpu, tidle);
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}
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static inline int __cpu_disable(void)
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{
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return smp_ops.cpu_disable();
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}
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static inline void __cpu_die(unsigned int cpu)
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{
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smp_ops.cpu_die(cpu);
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}
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static inline void play_dead(void)
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{
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smp_ops.play_dead();
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}
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static inline void smp_send_reschedule(int cpu)
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{
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smp_ops.smp_send_reschedule(cpu);
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}
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static inline void arch_send_call_function_single_ipi(int cpu)
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{
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smp_ops.send_call_func_single_ipi(cpu);
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}
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static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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{
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smp_ops.send_call_func_ipi(mask);
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}
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void cpu_disable_common(void);
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void native_smp_prepare_boot_cpu(void);
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void native_smp_prepare_cpus(unsigned int max_cpus);
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void native_smp_cpus_done(unsigned int max_cpus);
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void common_cpu_up(unsigned int cpunum, struct task_struct *tidle);
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int native_cpu_up(unsigned int cpunum, struct task_struct *tidle);
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int native_cpu_disable(void);
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int common_cpu_die(unsigned int cpu);
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void native_cpu_die(unsigned int cpu);
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void hlt_play_dead(void);
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void native_play_dead(void);
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void play_dead_common(void);
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void wbinvd_on_cpu(int cpu);
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int wbinvd_on_all_cpus(void);
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void native_send_call_func_ipi(const struct cpumask *mask);
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void native_send_call_func_single_ipi(int cpu);
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void x86_idle_thread_init(unsigned int cpu, struct task_struct *idle);
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void smp_store_boot_cpu_info(void);
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void smp_store_cpu_info(int id);
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#define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu)
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#else /* !CONFIG_SMP */
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#define wbinvd_on_cpu(cpu) wbinvd()
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static inline int wbinvd_on_all_cpus(void)
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{
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wbinvd();
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return 0;
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}
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#define smp_num_siblings 1
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#endif /* CONFIG_SMP */
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extern unsigned disabled_cpus;
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#ifdef CONFIG_X86_32_SMP
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/*
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* This function is needed by all SMP systems. It must _always_ be valid
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* from the initial startup. We map APIC_BASE very early in page_setup(),
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* so this is correct in the x86 case.
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*/
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#define raw_smp_processor_id() (this_cpu_read(cpu_number))
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extern int safe_smp_processor_id(void);
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#elif defined(CONFIG_X86_64_SMP)
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#define raw_smp_processor_id() (this_cpu_read(cpu_number))
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#define stack_smp_processor_id() \
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({ \
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struct thread_info *ti; \
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__asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
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ti->cpu; \
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})
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#define safe_smp_processor_id() smp_processor_id()
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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#ifndef CONFIG_X86_64
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static inline int logical_smp_processor_id(void)
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{
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/* we don't want to mark this access volatile - bad code generation */
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return GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
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}
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#endif
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extern int hard_smp_processor_id(void);
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#else /* CONFIG_X86_LOCAL_APIC */
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# ifndef CONFIG_SMP
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# define hard_smp_processor_id() 0
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# endif
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#endif /* CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_DEBUG_NMI_SELFTEST
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extern void nmi_selftest(void);
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#else
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#define nmi_selftest() do { } while (0)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_X86_SMP_H */
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