4aa705b18b
Pull ARM SoC platform support updates from Kevin Hilman: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits) ARM: zx: Add basic defconfig support for ZX296702 ARM: dts: zx: add an initial zx296702 dts and doc clk: zx: add clock support to zx296702 dt-bindings: Add #defines for ZTE ZX296702 clocks ARM: socfpga: fix build error due to secondary_startup MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS ARM: ep93xx: simone: support for SPI-based MMC/SD cards MAINTAINERS: update Shawn's email to use kernel.org one ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 ARM: EXYNOS: register power domain driver from core_initcall ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs ARM: SAMSUNG: Constify platform_device_id ARM: EXYNOS: Constify irq_domain_ops ARM: EXYNOS: add coupled cpuidle support for Exynos3250 ARM: EXYNOS: add exynos_get_boot_addr() helper ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ...
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/*
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* This file contains common function prototypes to avoid externs
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* in the c files.
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_ZYNQ_COMMON_H__
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#define __MACH_ZYNQ_COMMON_H__
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extern int zynq_slcr_init(void);
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extern int zynq_early_slcr_init(void);
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extern void zynq_slcr_cpu_stop(int cpu);
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extern void zynq_slcr_cpu_start(int cpu);
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extern bool zynq_slcr_cpu_state_read(int cpu);
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extern void zynq_slcr_cpu_state_write(int cpu, bool die);
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extern u32 zynq_slcr_get_device_id(void);
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#ifdef CONFIG_SMP
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extern char zynq_secondary_trampoline;
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extern char zynq_secondary_trampoline_jump;
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extern char zynq_secondary_trampoline_end;
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extern int zynq_cpun_start(u32 address, int cpu);
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extern struct smp_operations zynq_smp_ops __initdata;
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#endif
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extern void __iomem *zynq_scu_base;
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void zynq_pm_late_init(void);
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static inline void zynq_core_pm_init(void)
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{
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/* A9 clock gating */
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asm volatile ("mrc p15, 0, r12, c15, c0, 0\n"
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"orr r12, r12, #1\n"
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"mcr p15, 0, r12, c15, c0, 0\n"
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: /* no outputs */
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: /* no inputs */
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: "r12");
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}
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#endif
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