2f9ac29eec
This change enables unaligned userspace memory access via a kernel fast path on tilegx. The kernel tracks user PC/instruction pairs per-thread using a direct-mapped cache in userspace. The cache maps those PC/instruction pairs to JIT'ed instruction sequences that load or store using byte-wide load store intructions and then synthesize 2-, 4- or 8-byte load or store results. Once an instruction has been seen to generate an unaligned access once, subsequent hits on that instruction typically require overhead of only around 50 cycles if cache and TLB is hot. We support the prctl() PR_GET_UNALIGN / PR_SET_UNALIGN sys call to enable or disable unaligned fixups on a per-process basis. To do this we pull some of the tilepro unaligned support out of the single_step.c file; tilepro uses instruction disassembly for both single-step and unaligned access support. Since tilegx actually has hardware singlestep support, though, it's cleaner to keep the tilegx unaligned access code in a separate file. While we're at it, properly rename the tilepro-specific types, etc., to have tilepro suffixes instead of generic tile suffixes. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_PTRACE_H
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#define _ASM_TILE_PTRACE_H
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#include <linux/compiler.h>
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#ifndef __ASSEMBLY__
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/* Benefit from consistent use of "long" on all chips. */
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typedef unsigned long pt_reg_t;
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#endif
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#include <uapi/asm/ptrace.h>
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#define PTRACE_O_MASK_TILE (PTRACE_O_TRACEMIGRATE)
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#define PT_TRACE_MIGRATE PT_EVENT_FLAG(PTRACE_EVENT_MIGRATE)
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/* Flag bits in pt_regs.flags */
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#define PT_FLAGS_DISABLE_IRQ 1 /* on return to kernel, disable irqs */
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#define PT_FLAGS_CALLER_SAVES 2 /* caller-save registers are valid */
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#define PT_FLAGS_RESTORE_REGS 4 /* restore callee-save regs on return */
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#ifndef __ASSEMBLY__
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#define instruction_pointer(regs) ((regs)->pc)
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#define profile_pc(regs) instruction_pointer(regs)
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#define user_stack_pointer(regs) ((regs)->sp)
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/* Does the process account for user or for system time? */
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#define user_mode(regs) (EX1_PL((regs)->ex1) == USER_PL)
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/* Fill in a struct pt_regs with the current kernel registers. */
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struct pt_regs *get_pt_regs(struct pt_regs *);
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/* Trace the current syscall. */
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extern int do_syscall_trace_enter(struct pt_regs *regs);
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extern void do_syscall_trace_exit(struct pt_regs *regs);
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#define arch_has_single_step() (1)
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/*
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* A structure for all single-stepper state.
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*
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* Also update defines in assembler section if it changes
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*/
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struct single_step_state {
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/* the page to which we will write hacked-up bundles */
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void __user *buffer;
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union {
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int flags;
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struct {
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unsigned long is_enabled:1, update:1, update_reg:6;
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};
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};
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unsigned long orig_pc; /* the original PC */
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unsigned long next_pc; /* return PC if no branch (PC + 1) */
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unsigned long branch_next_pc; /* return PC if we did branch/jump */
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unsigned long update_value; /* value to restore to update_target */
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};
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/* Single-step the instruction at regs->pc */
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extern void single_step_once(struct pt_regs *regs);
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/* Clean up after execve(). */
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extern void single_step_execve(void);
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struct task_struct;
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extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs);
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#ifdef __tilegx__
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/* We need this since sigval_t has a user pointer in it, for GETSIGINFO etc. */
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#define __ARCH_WANT_COMPAT_SYS_PTRACE
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#endif
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#endif /* !__ASSEMBLY__ */
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#define SINGLESTEP_STATE_MASK_IS_ENABLED 0x1
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#define SINGLESTEP_STATE_MASK_UPDATE 0x2
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#define SINGLESTEP_STATE_TARGET_LB 2
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#define SINGLESTEP_STATE_TARGET_UB 7
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#endif /* _ASM_TILE_PTRACE_H */
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