2f8501b9b8
The status register of the miscellaneous interrupt controller is 32 bits wide, but the actual value of NR_IRQS covers only 8 of them. Change NR_IRQS in order to make all of those interrupt lines usable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2441/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
37 lines
1.3 KiB
C
37 lines
1.3 KiB
C
/*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_ATH79_IRQ_H
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#define __ASM_MACH_ATH79_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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#define NR_IRQS 40
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#define ATH79_MISC_IRQ_BASE 8
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#define ATH79_MISC_IRQ_COUNT 32
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#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
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#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
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#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
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#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
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#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
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#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
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#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
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#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
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#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
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#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3)
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#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4)
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#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
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#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
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#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
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#include_next <irq.h>
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#endif /* __ASM_MACH_ATH79_IRQ_H */
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