james qian wang (Arm Technology China) 29e56aec91 drm/komeda: Add DT parsing ...

Parse DT and initialize corresponding dev/pipeline attributes.

Changes in v4:
- Rebase.

Changes in v3:
- Fixed style problem found by checkpatch.pl --strict.

Changes in v2:
- Unified abbreviation of "pipeline" to "pipe".

Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>

2019-01-14 11:09:37 +00:00

..

display

drm/komeda: Add DT parsing

2019-01-14 11:09:37 +00:00

hdlcd_crtc.c

drm/arm/hdlcd: Reject atomic commits that disable only the plane

2018-07-31 16:31:50 +01:00

hdlcd_drv.c

drm/arm/hdlcd: Use drm_fbdev_generic_setup()

2018-09-25 11:30:43 +02:00

hdlcd_drv.h

drm/arm/hdlcd: Use drm_fb_cma_fbdev_init/fini()

2018-07-31 16:31:50 +01:00

hdlcd_regs.h

drm: Add support for ARM's HDLCD controller.

2016-02-10 13:44:16 +00:00

Kconfig

drm/komeda: komeda_dev/pipeline/component definition and initialzation

2019-01-14 11:09:23 +00:00

Makefile

drm/komeda: komeda_dev/pipeline/component definition and initialzation

2019-01-14 11:09:23 +00:00

malidp_crtc.c

drm/arm/malidp: Validate rotations for compressed/uncompressed framebuffers for each layer

2018-10-02 12:11:00 +01:00

malidp_drv.c

drm: malidp: Add the size of the superblocks when calculating total

2018-10-05 15:39:51 +01:00

malidp_drv.h

drm/malidp: Enable MMU prefetch on Mali-DP650

2018-10-02 11:59:36 +01:00

malidp_hw.c

drm: mali-dp: Enable Mali-DP tiled buffer formats

2018-11-02 09:57:27 +00:00

malidp_hw.h

drm/arm/malidp: Implemented the size validation for AFBC framebuffers

2018-10-02 12:12:19 +01:00

malidp_mw.c

drm/malidp: Fix writeback in NV12

2018-10-02 11:54:26 +01:00

malidp_mw.h

drm: mali-dp: Add writeback connector

2018-07-05 15:19:03 +01:00

malidp_planes.c

drm: mali-dp: Enable Mali-DP tiled buffer formats

2018-11-02 09:57:27 +00:00

malidp_regs.h

drm/malidp: Enable MMU prefetch on Mali-DP650

2018-10-02 11:59:36 +01:00