8bb0148955
CDCLK can either be an output generated by the CPU, intended for use as the CODEC master clock, or an input (probably from the CODEC) providing a master clock for the IIS block. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
83 lines
2.8 KiB
C
83 lines
2.8 KiB
C
/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
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*
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* Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2412 IIS register definition
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*/
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#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
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#define __ASM_ARCH_REGS_S3C2412_IIS_H
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#define S3C2412_IISCON (0x00)
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#define S3C2412_IISMOD (0x04)
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#define S3C2412_IISFIC (0x08)
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#define S3C2412_IISPSR (0x0C)
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#define S3C2412_IISTXD (0x10)
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#define S3C2412_IISRXD (0x14)
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#define S3C2412_IISCON_LRINDEX (1 << 11)
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#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)
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#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)
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#define S3C2412_IISCON_TXFIFO_FULL (1 << 8)
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#define S3C2412_IISCON_RXFIFO_FULL (1 << 7)
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#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6)
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#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5)
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#define S3C2412_IISCON_TXCH_PAUSE (1 << 4)
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#define S3C2412_IISCON_RXCH_PAUSE (1 << 3)
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#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)
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#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)
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#define S3C2412_IISCON_IIS_ACTIVE (1 << 0)
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#define S3C64XX_IISMOD_BLC_16BIT (0 << 13)
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#define S3C64XX_IISMOD_BLC_8BIT (1 << 13)
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#define S3C64XX_IISMOD_BLC_24BIT (2 << 13)
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#define S3C64XX_IISMOD_BLC_MASK (3 << 13)
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#define S3C64XX_IISMOD_IMS_PCLK (0 << 10)
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#define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10)
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#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10)
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#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10)
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#define S3C2412_IISMOD_SLAVE (2 << 10)
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#define S3C2412_IISMOD_MASTER_MASK (3 << 10)
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#define S3C2412_IISMOD_MODE_TXONLY (0 << 8)
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#define S3C2412_IISMOD_MODE_RXONLY (1 << 8)
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#define S3C2412_IISMOD_MODE_TXRX (2 << 8)
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#define S3C2412_IISMOD_MODE_MASK (3 << 8)
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#define S3C2412_IISMOD_LR_LLOW (0 << 7)
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#define S3C2412_IISMOD_LR_RLOW (1 << 7)
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#define S3C2412_IISMOD_SDF_IIS (0 << 5)
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#define S3C2412_IISMOD_SDF_MSB (1 << 5)
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#define S3C2412_IISMOD_SDF_LSB (2 << 5)
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#define S3C2412_IISMOD_SDF_MASK (3 << 5)
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#define S3C2412_IISMOD_RCLK_256FS (0 << 3)
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#define S3C2412_IISMOD_RCLK_512FS (1 << 3)
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#define S3C2412_IISMOD_RCLK_384FS (2 << 3)
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#define S3C2412_IISMOD_RCLK_768FS (3 << 3)
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#define S3C2412_IISMOD_RCLK_MASK (3 << 3)
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#define S3C2412_IISMOD_BCLK_32FS (0 << 1)
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#define S3C2412_IISMOD_BCLK_48FS (1 << 1)
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#define S3C2412_IISMOD_BCLK_16FS (2 << 1)
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#define S3C2412_IISMOD_BCLK_24FS (3 << 1)
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#define S3C2412_IISMOD_BCLK_MASK (3 << 1)
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#define S3C2412_IISMOD_8BIT (1 << 0)
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#define S3C64XX_IISMOD_CDCLKCON (1 << 12)
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#define S3C2412_IISPSR_PSREN (1 << 15)
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#define S3C2412_IISFIC_TXFLUSH (1 << 15)
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#define S3C2412_IISFIC_RXFLUSH (1 << 7)
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#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf)
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#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf)
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#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
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