22e9c88d48
This patch drops the assembly PPC64 version of flush_dcache_range()
and re-uses the PPC32 static inline version.
With GCC 8.1, the following code is generated:
void flush_test(unsigned long start, unsigned long stop)
{
flush_dcache_range(start, stop);
}
0000000000000130 <.flush_test>:
130: 3d 22 00 00 addis r9,r2,0
132: R_PPC64_TOC16_HA .data+0x8
134: 81 09 00 00 lwz r8,0(r9)
136: R_PPC64_TOC16_LO .data+0x8
138: 3d 22 00 00 addis r9,r2,0
13a: R_PPC64_TOC16_HA .data+0xc
13c: 80 e9 00 00 lwz r7,0(r9)
13e: R_PPC64_TOC16_LO .data+0xc
140: 7d 48 00 d0 neg r10,r8
144: 7d 43 18 38 and r3,r10,r3
148: 7c 00 04 ac hwsync
14c: 4c 00 01 2c isync
150: 39 28 ff ff addi r9,r8,-1
154: 7c 89 22 14 add r4,r9,r4
158: 7c 83 20 50 subf r4,r3,r4
15c: 7c 89 3c 37 srd. r9,r4,r7
160: 41 82 00 1c beq 17c <.flush_test+0x4c>
164: 7d 29 03 a6 mtctr r9
168: 60 00 00 00 nop
16c: 60 00 00 00 nop
170: 7c 00 18 ac dcbf 0,r3
174: 7c 63 42 14 add r3,r3,r8
178: 42 00 ff f8 bdnz 170 <.flush_test+0x40>
17c: 7c 00 04 ac hwsync
180: 4c 00 01 2c isync
184: 4e 80 00 20 blr
188: 60 00 00 00 nop
18c: 60 00 00 00 nop
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_CACHEFLUSH_H
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#define _ASM_POWERPC_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/cputable.h>
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/*
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* No cache flushing is required when address mappings are changed,
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* because the caches on PowerPCs are physically addressed.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* Book3s has no ptesync after setting a pte, so without this ptesync it's
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* possible for a kernel virtual mapping access to return a spurious fault
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* if it's accessed right after the pte is set. The page fault handler does
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* not expect this type of fault. flush_cache_vmap is not exactly the right
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* place to put this, but it seems to work well enough.
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*/
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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asm volatile("ptesync" ::: "memory");
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}
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#else
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static inline void flush_cache_vmap(unsigned long start, unsigned long end) { }
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#endif
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void flush_icache_range(unsigned long, unsigned long);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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extern void __flush_dcache_icache(void *page_va);
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extern void flush_dcache_icache_page(struct page *page);
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#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
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extern void __flush_dcache_icache_phys(unsigned long physaddr);
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#else
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static inline void __flush_dcache_icache_phys(unsigned long physaddr)
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{
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BUG();
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}
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#endif
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*/
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static inline void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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unsigned long shift = l1_cache_shift();
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unsigned long bytes = l1_cache_bytes();
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void *addr = (void *)(start & ~(bytes - 1));
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unsigned long size = stop - (unsigned long)addr + (bytes - 1);
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unsigned long i;
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if (IS_ENABLED(CONFIG_PPC64)) {
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mb(); /* sync */
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isync();
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}
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for (i = 0; i < size >> shift; i++, addr += bytes)
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dcbf(addr);
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mb(); /* sync */
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if (IS_ENABLED(CONFIG_PPC64))
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isync();
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}
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/*
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* Write any modified data cache blocks out to memory.
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* Does not invalidate the corresponding cache lines (especially for
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* any corresponding instruction cache).
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*/
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static inline void clean_dcache_range(unsigned long start, unsigned long stop)
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{
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unsigned long shift = l1_cache_shift();
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unsigned long bytes = l1_cache_bytes();
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void *addr = (void *)(start & ~(bytes - 1));
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unsigned long size = stop - (unsigned long)addr + (bytes - 1);
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unsigned long i;
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for (i = 0; i < size >> shift; i++, addr += bytes)
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dcbst(addr);
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mb(); /* sync */
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}
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*/
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static inline void invalidate_dcache_range(unsigned long start,
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unsigned long stop)
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{
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unsigned long shift = l1_cache_shift();
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unsigned long bytes = l1_cache_bytes();
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void *addr = (void *)(start & ~(bytes - 1));
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unsigned long size = stop - (unsigned long)addr + (bytes - 1);
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unsigned long i;
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for (i = 0; i < size >> shift; i++, addr += bytes)
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dcbi(addr);
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mb(); /* sync */
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}
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHEFLUSH_H */
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