1f85b42a69
Commit 9730348075 ("arm64: Increase the max granular size") increased
the cache line size to 128 to match Cavium ThunderX, apparently for some
performance benefit which could not be confirmed. This change, however,
has an impact on the network packets allocation in certain
circumstances, requiring slightly over a 4K page with a significant
performance degradation.
This patch reverts L1_CACHE_SHIFT back to 6 (64-byte cache line) while
keeping ARCH_DMA_MINALIGN at 128. The cache_line_size() function was
changed to default to ARCH_DMA_MINALIGN in the absence of a meaningful
CTR_EL0.CWG bit field.
In addition, if a system with ARCH_DMA_MINALIGN < CTR_EL0.CWG is
detected, the kernel will force swiotlb bounce buffering for all
non-coherent devices since DMA cache maintenance on sub-CWG ranges is
not safe, leading to data corruption.
Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Cc: Timur Tabi <timur@codeaurora.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CACHE_H
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#define __ASM_CACHE_H
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#include <asm/cputype.h>
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#define CTR_L1IP_SHIFT 14
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#define CTR_L1IP_MASK 3
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#define CTR_CWG_SHIFT 24
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#define CTR_CWG_MASK 15
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#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
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#define ICACHE_POLICY_VPIPT 0
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#define ICACHE_POLICY_VIPT 2
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#define ICACHE_POLICY_PIPT 3
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#define L1_CACHE_SHIFT (6)
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/*
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* Memory returned by kmalloc() may be used for DMA, so we must make
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* sure that all such allocations are cache aligned. Otherwise,
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* unrelated code may cause parts of the buffer to be read into the
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* cache before the transfer is done, causing old data to be seen by
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* the CPU.
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*/
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#define ARCH_DMA_MINALIGN (128)
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#define ICACHEF_ALIASING 0
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#define ICACHEF_VPIPT 1
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extern unsigned long __icache_flags;
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/*
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* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
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* permitted in the I-cache.
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*/
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static inline int icache_is_aliasing(void)
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{
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return test_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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static inline int icache_is_vpipt(void)
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{
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return test_bit(ICACHEF_VPIPT, &__icache_flags);
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}
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static inline u32 cache_type_cwg(void)
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{
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return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
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}
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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static inline int cache_line_size(void)
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{
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u32 cwg = cache_type_cwg();
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return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
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}
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#endif /* __ASSEMBLY__ */
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#endif
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