1e8937526e
Most architectures do not support non-coherent allocations and either
define dma_{alloc,free}_noncoherent to their coherent versions or stub
them out.
Openrisc uses dma_{alloc,free}_attrs to implement them, and only Mips
implements them directly.
This patch moves the Openrisc version to common code, and handles the
DMA_ATTR_NON_CONSISTENT case in the mips dma_map_ops instance.
Note that actual non-coherent allocations require a dma_cache_sync
implementation, so if non-coherent allocations didn't work on
an architecture before this patch they still won't work after it.
[jcmvbkbc@gmail.com: fix xtensa]
Signed-off-by: Christoph Hellwig <hch@lst.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Jonas Bonn <jonas@southpole.se>
Cc: Chris Metcalf <cmetcalf@ezchip.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
128 lines
3.1 KiB
C
128 lines
3.1 KiB
C
#ifndef _ASM_X86_DMA_MAPPING_H
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#define _ASM_X86_DMA_MAPPING_H
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/*
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* IOMMU interface. See Documentation/DMA-API-HOWTO.txt and
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* Documentation/DMA-API.txt for documentation.
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*/
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#include <linux/kmemcheck.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-debug.h>
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#include <linux/dma-attrs.h>
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#include <asm/io.h>
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#include <asm/swiotlb.h>
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#include <linux/dma-contiguous.h>
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#ifdef CONFIG_ISA
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
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#else
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
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#endif
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#define DMA_ERROR_CODE 0
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extern int iommu_merge;
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extern struct device x86_dma_fallback_dev;
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extern int panic_on_overflow;
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extern struct dma_map_ops *dma_ops;
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static inline struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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#ifndef CONFIG_X86_DEV_DMA_OPS
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return dma_ops;
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#else
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if (unlikely(!dev) || !dev->archdata.dma_ops)
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return dma_ops;
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else
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return dev->archdata.dma_ops;
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#endif
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}
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bool arch_dma_alloc_attrs(struct device **dev, gfp_t *gfp);
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#define arch_dma_alloc_attrs arch_dma_alloc_attrs
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#include <asm-generic/dma-mapping-common.h>
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/* Make sure we keep the same behaviour */
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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struct dma_map_ops *ops = get_dma_ops(dev);
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debug_dma_mapping_error(dev, dma_addr);
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if (ops->mapping_error)
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return ops->mapping_error(dev, dma_addr);
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return (dma_addr == DMA_ERROR_CODE);
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}
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extern int dma_supported(struct device *hwdev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 mask);
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extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addr, gfp_t flag,
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struct dma_attrs *attrs);
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extern void dma_generic_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_addr,
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struct dma_attrs *attrs);
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#ifdef CONFIG_X86_DMA_REMAP /* Platform code defines bridge-specific code */
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extern bool dma_capable(struct device *dev, dma_addr_t addr, size_t size);
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extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
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extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
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#else
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (!dev->dma_mask)
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return 0;
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return addr + size - 1 <= *dev->dma_mask;
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}
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr;
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}
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static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return daddr;
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}
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#endif /* CONFIG_X86_DMA_REMAP */
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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flush_write_buffers();
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}
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static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
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gfp_t gfp)
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{
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unsigned long dma_mask = 0;
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dma_mask = dev->coherent_dma_mask;
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if (!dma_mask)
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dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);
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return dma_mask;
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}
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static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
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{
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unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
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if (dma_mask <= DMA_BIT_MASK(24))
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gfp |= GFP_DMA;
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#ifdef CONFIG_X86_64
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if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
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gfp |= GFP_DMA32;
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#endif
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return gfp;
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}
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#endif
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