6a6273a65f
[ Upstream commit eab696d8e8b9c9d600be6fad8dd8dfdfaca6ca7c ] A malicious hypervisor could disable the CPUID intercept for an SEV or SEV-ES guest and trick it into the no-SEV boot path, where it could potentially reveal secrets. This is not an issue for SEV-SNP guests, as the CPUID intercept can't be disabled for those. Remove the Hypervisor CPUID bit check from the SEV detection code to protect against this kind of attack and add a Hypervisor bit equals zero check to the SME detection path to prevent non-encrypted guests from trying to enable SME. This handles the following cases: 1) SEV(-ES) guest where CPUID intercept is disabled. The guest will still see leaf 0x8000001f and the SEV bit. It can retrieve the C-bit and boot normally. 2) Non-encrypted guests with intercepted CPUID will check the SEV_STATUS MSR and find it 0 and will try to enable SME. This will fail when the guest finds MSR_K8_SYSCFG to be zero, as it is emulated by KVM. But we can't rely on that, as there might be other hypervisors which return this MSR with bit 23 set. The Hypervisor bit check will prevent that the guest tries to enable SME in this case. 3) Non-encrypted guests on SEV capable hosts with CPUID intercept disabled (by a malicious hypervisor) will try to boot into the SME path. This will fail, but it is also not considered a problem because non-encrypted guests have no protection against the hypervisor anyway. [ bp: s/non-SEV/non-encrypted/g ] Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lkml.kernel.org/r/20210312123824.306-3-joro@8bytes.org Signed-off-by: Sasha Levin <sashal@kernel.org>
113 lines
2.2 KiB
ArmAsm
113 lines
2.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AMD Memory Encryption Support
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#include <linux/linkage.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <asm/asm-offsets.h>
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.text
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.code32
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SYM_FUNC_START(get_sev_encryption_bit)
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xor %eax, %eax
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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push %ebx
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push %ecx
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push %edx
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movl $0x80000000, %eax /* CPUID to check the highest leaf */
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cpuid
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cmpl $0x8000001f, %eax /* See if 0x8000001f is available */
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jb .Lno_sev
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/*
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* Check for the SEV feature:
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* CPUID Fn8000_001F[EAX] - Bit 1
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* CPUID Fn8000_001F[EBX] - Bits 5:0
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* Pagetable bit position used to indicate encryption
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*/
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movl $0x8000001f, %eax
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cpuid
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bt $1, %eax /* Check if SEV is available */
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jnc .Lno_sev
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movl $MSR_AMD64_SEV, %ecx /* Read the SEV MSR */
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rdmsr
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bt $MSR_AMD64_SEV_ENABLED_BIT, %eax /* Check if SEV is active */
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jnc .Lno_sev
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movl %ebx, %eax
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andl $0x3f, %eax /* Return the encryption bit location */
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jmp .Lsev_exit
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.Lno_sev:
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xor %eax, %eax
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.Lsev_exit:
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pop %edx
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pop %ecx
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pop %ebx
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#endif /* CONFIG_AMD_MEM_ENCRYPT */
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ret
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SYM_FUNC_END(get_sev_encryption_bit)
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.code64
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#include "../../kernel/sev_verify_cbit.S"
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SYM_FUNC_START(set_sev_encryption_mask)
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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push %rbp
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push %rdx
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movq %rsp, %rbp /* Save current stack pointer */
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call get_sev_encryption_bit /* Get the encryption bit position */
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testl %eax, %eax
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jz .Lno_sev_mask
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bts %rax, sme_me_mask(%rip) /* Create the encryption mask */
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/*
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* Read MSR_AMD64_SEV again and store it to sev_status. Can't do this in
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* get_sev_encryption_bit() because this function is 32-bit code and
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* shared between 64-bit and 32-bit boot path.
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*/
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movl $MSR_AMD64_SEV, %ecx /* Read the SEV MSR */
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rdmsr
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/* Store MSR value in sev_status */
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shlq $32, %rdx
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orq %rdx, %rax
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movq %rax, sev_status(%rip)
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.Lno_sev_mask:
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movq %rbp, %rsp /* Restore original stack pointer */
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pop %rdx
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pop %rbp
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#endif
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xor %rax, %rax
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ret
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SYM_FUNC_END(set_sev_encryption_mask)
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.data
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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.balign 8
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SYM_DATA(sme_me_mask, .quad 0)
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SYM_DATA(sev_status, .quad 0)
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SYM_DATA(sev_check_data, .quad 0)
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#endif
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