Files
android_kernel_xiaomi_sm8450/drivers/pci/controller/dwc
Martin Blumenstingl 12d84de59d PCI: intel-gw: Fix INTx enable
[ Upstream commit 655832d12f2251e04031294f547c86935a0a126d ]

The legacy PCI interrupt lines need to be enabled using PCIE_APP_IRNEN bits
13 (INTA), 14 (INTB), 15 (INTC) and 16 (INTD). The old code however was
taking (for example) "13" as raw value instead of taking BIT(13).  Define
the legacy PCI interrupt bits using the BIT() macro and then use these in
PCIE_APP_IRN_INT.

Link: https://lore.kernel.org/r/20210106135540.48420-1-martin.blumenstingl@googlemail.com
Fixes: ed22aaaede ("PCI: dwc: intel: PCIe RC controller driver")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rahul Tanwar <rtanwar@maxlinear.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-20 16:05:52 +02:00
..
2020-10-05 13:01:42 +01:00
2020-08-05 18:24:22 -05:00
2021-07-20 16:05:52 +02:00
2020-09-10 16:50:53 +01:00