11d73c56b9
This cleanup series gets rid of <mach/timex.h> for platforms not using
ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since
387798b (ARM: initial multiplatform support).)
To make this work some code out of arch/arm needed to be adapted. The
respective changes got acks by their maintainers to be taken via armsoc
(with Andrew Morton substituting for Alessandro Zummo as rtc maintainer).
Compared to the previous pull request there was another patch added that
fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not
squash this fix into the original commit to save him from the need to
reverify the series.
* tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux:
ARM: ixp4xx: fix timer latch calculation
ARM: drop <mach/timex.h> for !ARCH_MULTIPLATFORM, too
ARM: rpc: stop using <mach/timex.h>
ARM: ixp4xx: stop using <mach/timex.h>
input: ixp4xx-beeper: don't use symbols from <mach/timex.h>
ARM: at91: don't use <mach/timex.h>
ARM: ep93xx: stop using mach/timex.h
ARM: mmp: stop using mach/timex.h
ARM: netx: stop using mach/timex.h
ARM: sa1100: stop using mach/timex.h
clocksource: sirf/marco+prima2: drop usage of CLOCK_TICK_RATE
rtc: pxa: drop unused #define TIMER_FREQ
rtc: at91sam9: include <mach/hardware.h> explicitly
ARM/serial: at91: switch atmel serial to use gpiolib
Signed-off-by: Olof Johansson <olof@lixom.net>
357 lines
9.0 KiB
C
357 lines
9.0 KiB
C
/*
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* arch/arm/mach-at91/at91sam9rl.c
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*
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* Copyright (C) 2005 SAN People
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* Copyright (C) 2007 Atmel Corporation
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/proc-fns.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include <mach/cpu.h>
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#include <mach/at91_dbgu.h>
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#include <mach/at91sam9rl.h>
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#include <mach/hardware.h>
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#include "at91_aic.h"
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#include "at91_rstc.h"
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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#include "pm.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioD_clk = {
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.name = "pioD_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi_clk = {
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.name = "spi_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tsc_clk = {
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.name = "tsc_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioD_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&mmc_clk,
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&twi0_clk,
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&twi1_clk,
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&spi_clk,
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&ssc0_clk,
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&ssc1_clk,
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&pwm_clk,
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&tsc_clk,
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&dma_clk,
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&udphs_clk,
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&lcdc_clk,
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&ac97_clk,
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// irq0
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
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CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
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CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
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CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
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CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
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CLKDEV_CON_ID("pioA", &pioA_clk),
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CLKDEV_CON_ID("pioB", &pioB_clk),
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CLKDEV_CON_ID("pioC", &pioC_clk),
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CLKDEV_CON_ID("pioD", &pioD_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9rl_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
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{
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.id = AT91SAM9RL_ID_PIOA,
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.regbase = AT91SAM9RL_BASE_PIOA,
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}, {
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.id = AT91SAM9RL_ID_PIOB,
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.regbase = AT91SAM9RL_BASE_PIOB,
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}, {
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.id = AT91SAM9RL_ID_PIOC,
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.regbase = AT91SAM9RL_BASE_PIOC,
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}, {
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.id = AT91SAM9RL_ID_PIOD,
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.regbase = AT91SAM9RL_BASE_PIOD,
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}
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};
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/* --------------------------------------------------------------------
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* AT91SAM9RL processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9rl_map_io(void)
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{
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unsigned long sram_size;
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switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
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case AT91_CIDR_SRAMSIZ_32K:
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sram_size = 2 * SZ_16K;
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break;
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case AT91_CIDR_SRAMSIZ_16K:
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default:
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sram_size = SZ_16K;
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}
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/* Map SRAM */
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at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
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}
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static void __init at91sam9rl_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
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at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
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at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
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at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
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at91_pm_set_standby(at91sam9_sdram_standby);
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}
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static void __init at91sam9rl_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
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at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9rl_gpio, 4);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface */
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6, /* Two-Wire Interface 0 */
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6, /* Two-Wire Interface 1 */
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5, /* Serial Peripheral Interface */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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0,
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0, /* Touch Screen Controller */
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0, /* DMA Controller */
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2, /* USB Device High speed port */
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2, /* LCD Controller */
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6, /* AC97 Controller */
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0,
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0,
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0,
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0,
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0,
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0,
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0, /* Advanced Interrupt Controller */
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};
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AT91_SOC_START(at91sam9rl)
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.map_io = at91sam9rl_map_io,
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.default_irq_priority = at91sam9rl_default_irq_priority,
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.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
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.ioremap_registers = at91sam9rl_ioremap_registers,
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.register_clocks = at91sam9rl_register_clocks,
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.init = at91sam9rl_initialize,
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AT91_SOC_END
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