320549a224
Commit 29bb45f25f (regmap-mmio: Use native endianness for read/write)
attempted to fix some long standing bugs in the MMIO implementation for
big endian systems caused by duplicate byte swapping in both regmap and
readl()/writel() which affected MIPS systems as when they are in big
endian mode they flip the endianness of all registers in the system, not
just the CPU. MIPS systems had worked around this by declaring regmap
using IPs as little endian which is inaccurate, unfortunately the issue
had not been reported.
Sadly the fix makes things worse rather than better. By changing the
behaviour to match the documentation it caused behaviour changes for
other IPs which broke them and by using the __raw I/O accessors to avoid
the endianness swapping in readl()/writel() it removed some memory
ordering guarantees and could potentially generate unvirtualisable
instructions on some architectures.
Unfortunately sorting out all this mess in any half way sensible fashion
was far too invasive to go in during an -rc cycle so instead let's go
back to the old broken behaviour for v4.5, the better fixes are already
queued for v4.6. This does mean that we keep the broken MIPS DTs for
another release but that seems the least bad way of handling the
situation.
Reported-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
246 lines
5.3 KiB
Plaintext
246 lines
5.3 KiB
Plaintext
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm7360";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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mips-hpt-frequency = <375000000>;
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cpu@0 {
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compatible = "brcm,bmips3300";
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device_type = "cpu";
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reg = <0>;
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};
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};
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aliases {
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uart0 = &uart0;
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uart1 = &uart1;
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uart2 = &uart2;
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};
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cpu_intc: cpu_intc {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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clocks {
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uart_clk: uart_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <81000000>;
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};
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};
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rdb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x10000000 0x01000000>;
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periph_intc: periph_intc@411400 {
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compatible = "brcm,bcm7038-l1-intc";
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reg = <0x411400 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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sun_l2_intc: sun_l2_intc@403000 {
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compatible = "brcm,l2-intc";
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reg = <0x403000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <48>;
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};
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gisb-arb@400000 {
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compatible = "brcm,bcm7400-gisb-arb";
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reg = <0x400000 0xdc>;
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native-endian;
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interrupt-parent = <&sun_l2_intc>;
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interrupts = <0>, <2>;
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brcm,gisb-arb-master-mask = <0x2f3>;
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brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
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"rdc_0", "raaga_0",
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"avd_0", "jtag_0";
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};
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upg_irq0_intc: upg_irq0_intc@406600 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x406600 0x8>;
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brcm,int-map-mask = <0x44>, <0x7000000>;
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brcm,int-fwd-mask = <0x70000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <56>, <54>;
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interrupt-names = "upg_main", "upg_bsc";
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};
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upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x408b80 0x8>;
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brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
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brcm,int-fwd-mask = <0>;
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brcm,irq-can-wake;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <57>, <55>, <59>;
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interrupt-names = "upg_main_aon", "upg_bsc_aon",
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"upg_spi";
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};
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sun_top_ctrl: syscon@404000 {
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compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
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reg = <0x404000 0x51c>;
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little-endian;
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};
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reboot {
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compatible = "brcm,brcmstb-reboot";
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syscon = <&sun_top_ctrl 0x304 0x308>;
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};
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uart0: serial@406800 {
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compatible = "ns16550a";
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reg = <0x406800 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <61>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@406840 {
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compatible = "ns16550a";
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reg = <0x406840 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <62>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@406880 {
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compatible = "ns16550a";
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reg = <0x406880 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <63>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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bsca: i2c@406200 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406200 0x58>;
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interrupts = <24>;
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interrupt-names = "upg_bsca";
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status = "disabled";
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};
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bscb: i2c@406280 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406280 0x58>;
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interrupts = <25>;
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interrupt-names = "upg_bscb";
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status = "disabled";
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};
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bscc: i2c@406300 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406300 0x58>;
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interrupts = <26>;
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interrupt-names = "upg_bscc";
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status = "disabled";
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};
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bscd: i2c@408980 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_aon_irq0_intc>;
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reg = <0x408980 0x58>;
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interrupts = <27>;
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interrupt-names = "upg_bscd";
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status = "disabled";
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};
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enet0: ethernet@430000 {
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phy-mode = "internal";
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phy-handle = <&phy1>;
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mac-address = [ 00 10 18 36 23 1a ];
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compatible = "brcm,genet-v2";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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reg = <0x430000 0x4c8c>;
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interrupts = <24>, <25>;
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interrupt-parent = <&periph_intc>;
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status = "disabled";
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mdio@e14 {
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compatible = "brcm,genet-mdio-v2";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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reg = <0xe14 0x8>;
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phy1: ethernet-phy@1 {
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max-speed = <100>;
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reg = <0x1>;
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compatible = "brcm,40nm-ephy",
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"ethernet-phy-ieee802.3-c22";
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};
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};
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};
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ehci0: usb@480300 {
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compatible = "brcm,bcm7360-ehci", "generic-ehci";
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reg = <0x480300 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <65>;
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status = "disabled";
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};
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ohci0: usb@480400 {
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compatible = "brcm,bcm7360-ohci", "generic-ohci";
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reg = <0x480400 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <66>;
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status = "disabled";
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};
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};
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};
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