xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
1172ee31259b51a9b2d83b05f01161fd5938b15d
android_kernel_xiaomi_sm8450/arch/arm/boot/dts/gemini.dtsi
Linus Torvalds 527d147074 Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 
Pull ARM device-tree updates from Arnd Bergmann:
 "We add device tree files for a couple of additional SoCs in various
  areas:

  Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for
  networking, Amlogic A113D for audio, and Renesas R-Car V3M for
  automotive.

  As usual, lots of new boards get added based on those and other SoCs:

   - Actions S500 based CubieBoard6 single-board computer

   - Amlogic Meson-AXG A113D based development board
   - Amlogic S912 based Khadas VIM2 single-board computer
   - Amlogic S912 based Tronsmart Vega S96 set-top-box

   - Allwinner H5 based NanoPi NEO Plus2 single-board computer
   - Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
   - Allwinner A83T based TBS A711 Tablet

   - Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
   - Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
     wireless access points and routers

   - NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
   - NXP i.MX53 based GE Healthcare PPD biometric monitor
   - NXP i.MX6 based Pistachio single-board computer
   - NXP i.MX6 based Vining-2000 automotive diagnostic interface
   - NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants

   - Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
   - Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet

   - Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA

   - Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
   - Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
   - Renasas r8a7745 based iWave G22D-SODIMM SoM

   - Rockchip rk3288 based Amarula Vyasa single-board computer

   - Samsung Exynos5800 based Odroid HC1 single-board computer

  For existing SoC support, there was a lot of ongoing work, as usual
  most of that concentrated on the Renesas, Rockchip, OMAP, i.MX,
  Amlogic and Allwinner platforms, but others were also active.

  Rob Herring and many others worked on reducing the number of issues
  that the latest version of 'dtc' now warns about. Unfortunately there
  is still a lot left to do.

  A rework of the ARM foundation model introduced several new files for
  common variations of the model"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits)
  arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
  dt-bindings: bus: Add documentation for the Technologic Systems NBUS
  arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
  ARM: dts: owl-s500: Add CubieBoard6
  dt-bindings: arm: actions: Add CubieBoard6
  ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock
  ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
  arm: dts: mt7623: remove unused compatible string for pio node
  arm: dts: mt7623: update usb related nodes
  arm: dts: mt7623: update crypto node
  ARM: dts: sun8i: a711: Enable USB OTG
  ARM: dts: sun8i: a711: Add regulator support
  ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
  ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
  ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
  ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
  ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
  ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
  ARM: dts: sunxi: Add dtsi for AXP81x PMIC
  arm64: dts: allwinner: H5: Restore EMAC changes
  ...
2017-11-16 15:48:26 -08:00

374 lines
9.5 KiB
Plaintext
Raw Blame History

// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for Cortina systems Gemini SoC
*/
/include/ "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/cortina,gemini-clock.h>
#include <dt-bindings/reset/cortina,gemini-reset.h>
#include <dt-bindings/gpio/gpio.h>
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
interrupt-parent = <&intcon>;
flash@30000000 {
compatible = "cortina,gemini-flash", "cfi-flash";
syscon = <&syscon>;
pinctrl-names = "default";
pinctrl-0 = <&pflash_default_pins>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
syscon: syscon@40000000 {
compatible = "cortina,gemini-syscon",
"syscon", "simple-mfd";
reg = <0x40000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
syscon-reboot {
compatible = "syscon-reboot";
regmap = <&syscon>;
/* GLOBAL_RESET register */
offset = <0x0c>;
/* RESET_GLOBAL | RESET_CPU1 */
mask = <0xC0000000>;
};
pinctrl {
compatible = "cortina,gemini-pinctrl";
regmap = <&syscon>;
/* Hog the DRAM pins */
pinctrl-names = "default";
pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
<&vcontrol_default_pins>;
dram_default_pins: pinctrl-dram {
mux {
function = "dram";
groups = "dramgrp";
};
};
rtc_default_pins: pinctrl-rtc {
mux {
function = "rtc";
groups = "rtcgrp";
};
};
power_default_pins: pinctrl-power {
mux {
function = "power";
groups = "powergrp";
};
};
cir_default_pins: pinctrl-cir {
mux {
function = "cir";
groups = "cirgrp";
};
};
system_default_pins: pinctrl-system {
mux {
function = "system";
groups = "systemgrp";
};
};
vcontrol_default_pins: pinctrl-vcontrol {
mux {
function = "vcontrol";
groups = "vcontrolgrp";
};
};
ice_default_pins: pinctrl-ice {
mux {
function = "ice";
groups = "icegrp";
};
};
uart_default_pins: pinctrl-uart {
mux {
function = "uart";
groups = "uartrxtxgrp";
};
};
pflash_default_pins: pinctrl-pflash {
mux {
function = "pflash";
groups = "pflashgrp";
};
};
usb_default_pins: pinctrl-usb {
mux {
function = "usb";
groups = "usbgrp";
};
};
gmii_default_pins: pinctrl-gmii {
mux {
function = "gmii";
groups = "gmiigrp";
};
};
pci_default_pins: pinctrl-pci {
mux {
function = "pci";
groups = "pcigrp";
};
};
sata_default_pins: pinctrl-sata {
mux {
function = "sata";
groups = "satagrp";
};
};
/* Activate both groups of pins for this state */
sata_and_ide_pins: pinctrl-sata-ide {
mux0 {
function = "sata";
groups = "satagrp";
};
mux1 {
function = "ide";
groups = "idegrp";
};
};
tvc_default_pins: pinctrl-tvc {
mux {
function = "tvc";
groups = "tvcgrp";
};
};
};
};
watchdog@41000000 {
compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
reg = <0x41000000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_WDOG>;
clocks = <&syscon GEMINI_CLK_APB>;
clock-names = "PCLK";
};
uart0: serial@42000000 {
compatible = "ns16550a";
reg = <0x42000000 0x100>;
resets = <&syscon GEMINI_RESET_UART>;
clocks = <&syscon GEMINI_CLK_UART>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart_default_pins>;
reg-shift = <2>;
};
timer@43000000 {
compatible = "faraday,fttmr010";
reg = <0x43000000 0x1000>;
interrupt-parent = <&intcon>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
resets = <&syscon GEMINI_RESET_TIMER>;
/* APB clock or RTC clock */
clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
clock-names = "PCLK", "EXTCLK";
syscon = <&syscon>;
};
rtc@45000000 {
compatible = "cortina,gemini-rtc";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_RTC>;
clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
clock-names = "PCLK", "EXTCLK";
pinctrl-names = "default";
pinctrl-0 = <&rtc_default_pins>;
};
sata: sata@46000000 {
compatible = "cortina,gemini-sata-bridge";
reg = <0x46000000 0x100>;
resets = <&syscon GEMINI_RESET_SATA0>,
<&syscon GEMINI_RESET_SATA1>;
reset-names = "sata0", "sata1";
clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
<&syscon GEMINI_CLK_GATE_SATA1>;
clock-names = "SATA0_PCLK", "SATA1_PCLK";
/*
* This defines the special "ide" state that needs
* to be explicitly enabled to enable the IDE pins,
* as these pins are normally used for other things.
*/
pinctrl-names = "default", "ide";
pinctrl-0 = <&sata_default_pins>;
pinctrl-1 = <&sata_and_ide_pins>;
syscon = <&syscon>;
status = "disabled";
};
intcon: interrupt-controller@48000000 {
compatible = "faraday,ftintc010";
reg = <0x48000000 0x1000>;
resets = <&syscon GEMINI_RESET_INTCON0>;
interrupt-controller;
#interrupt-cells = <2>;
};
power-controller@4b000000 {
compatible = "cortina,gemini-power-controller";
reg = <0x4b000000 0x100>;
interrupts = <26 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&power_default_pins>;
};
gpio0: gpio@4d000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4d000000 0x100>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GPIO0>;
clocks = <&syscon GEMINI_CLK_APB>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@4e000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4e000000 0x100>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GPIO1>;
clocks = <&syscon GEMINI_CLK_APB>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@4f000000 {
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4f000000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GPIO2>;
clocks = <&syscon GEMINI_CLK_APB>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pci@50000000 {
compatible = "cortina,gemini-pci", "faraday,ftpci100";
/*
* The first 256 bytes in the IO range is actually used
* to configure the host bridge.
*/
reg = <0x50000000 0x100>;
resets = <&syscon GEMINI_RESET_PCI>;
clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
clock-names = "PCLK", "PCICLK";
pinctrl-names = "default";
pinctrl-0 = <&pci_default_pins>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
status = "disabled";
bus-range = <0x00 0xff>;
/* PCI ranges mappings */
ranges =
/* 1MiB I/O space 0x50000000-0x500fffff */
<0x01000000 0 0 0x50000000 0 0x00100000>,
/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
/* DMA ranges */
dma-ranges =
/* 128MiB at 0x00000000-0x07ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
/* 64MiB at 0x00000000-0x03ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
/* 64MiB at 0x00000000-0x03ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
/*
* This PCI host bridge variant has a cascaded interrupt
* controller embedded in the host bridge.
*/
pci_intc: interrupt-controller {
interrupt-parent = <&intcon>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
ata@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
resets = <&syscon GEMINI_RESET_IDE>;
clocks = <&syscon GEMINI_CLK_GATE_IDE>;
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
};
ata@63400000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63400000 0x1000>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
resets = <&syscon GEMINI_RESET_IDE>;
clocks = <&syscon GEMINI_CLK_GATE_IDE>;
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
};
dma-controller@67000000 {
compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
/* Faraday Technology FTDMAC020 variant */
arm,primecell-periphid = <0x0003b080>;
reg = <0x67000000 0x1000>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
resets = <&syscon GEMINI_RESET_DMAC>;
clocks = <&syscon GEMINI_CLK_AHB>;
clock-names = "apb_pclk";
/* Bus interface AHB1 (AHB0) is totally tilted */
lli-bus-interface-ahb2;
mem-bus-interface-ahb2;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
#dma-cells = <2>;
};
display-controller@6a000000 {
compatible = "cortina,gemini-tvc", "faraday,tve200";
reg = <0x6a000000 0x1000>;
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
resets = <&syscon GEMINI_RESET_TVC>;
clocks = <&syscon GEMINI_CLK_GATE_TVC>,
<&syscon GEMINI_CLK_TVC>;
clock-names = "PCLK", "TVE";
pinctrl-names = "default";
pinctrl-0 = <&tvc_default_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
Reference in New Issue View Git Blame Copy Permalink