755a9ba7bf
Pull ARM SoC devicetree updates from Olof Johansson: "As with previous release, this continues to be among the largest branches we merge, with lots of new contents. New things for this release are among other things: - DTSI contents for the new SoCs supported in 3.16 (see SoC pull request) - Qualcomm APQ8064 and APQ8084 SoCs and eval boards - Nvidia Jetson TK1 development board (Tegra T124-based) Two new SoCs that didn't need enough new platform code to stand out enough for me to notice when writing the SoC tag, but that adds new DT contents are: - TI DRA72 - Marvell Berlin 2Q" * tag 'dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (500 commits) ARM: dts: add secure firmware support for exynos5420-arndale-octa ARM: dts: add pmu sysreg node to exynos3250 ARM: dts: correct the usb phy node in exynos5800-peach-pi ARM: dts: correct the usb phy node in exynos5420-peach-pit ARM: dts: add dts files for exynos5410 and exynos5410-smdk5410 ARM: dts: add dts files for exynos3250 SoC ARM: dts: add mfc node for exynos5800 ARM: dts: add Vbus regulator for USB 3.0 on exynos5800-peach-pi ARM: dts: enable fimd for exynos5800-peach-pi ARM: dts: enable display controller for exynos5800-peach-pi ARM: dts: enable hdmi for exynos5800-peach-pi ARM: dts: add dts file for exynos5800-peach-pi board ARM: dts: add dts file for exynos5800 SoC ARM: dts: add dts file for exynos5260-xyref5260 board ARM: dts: add dts files for exynos5260 SoC ARM: dts: update watchdog node name in exynos5440 ARM: dts: use key code macros on Origen and Arndale boards ARM: dts: enable RTC and WDT nodes on Origen boards ARM: dts: qcom: Add APQ8084-MTP board support ARM: dts: qcom: Add APQ8084 SoC support ...
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* Copyright 2013 Ideas On Board SPRL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
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#define __DT_BINDINGS_CLOCK_R8A7790_H__
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/* CPG */
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#define R8A7790_CLK_MAIN 0
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#define R8A7790_CLK_PLL0 1
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#define R8A7790_CLK_PLL1 2
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#define R8A7790_CLK_PLL3 3
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#define R8A7790_CLK_LB 4
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#define R8A7790_CLK_QSPI 5
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#define R8A7790_CLK_SDH 6
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#define R8A7790_CLK_SD0 7
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#define R8A7790_CLK_SD1 8
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#define R8A7790_CLK_Z 9
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/* MSTP0 */
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#define R8A7790_CLK_MSIOF0 0
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/* MSTP1 */
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#define R8A7790_CLK_TMU1 11
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#define R8A7790_CLK_TMU3 21
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#define R8A7790_CLK_TMU2 22
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#define R8A7790_CLK_CMT0 24
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#define R8A7790_CLK_TMU0 25
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#define R8A7790_CLK_VSP1_DU1 27
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#define R8A7790_CLK_VSP1_DU0 28
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#define R8A7790_CLK_VSP1_R 30
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#define R8A7790_CLK_VSP1_S 31
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/* MSTP2 */
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#define R8A7790_CLK_SCIFA2 2
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#define R8A7790_CLK_SCIFA1 3
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#define R8A7790_CLK_SCIFA0 4
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#define R8A7790_CLK_MSIOF2 5
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#define R8A7790_CLK_SCIFB0 6
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#define R8A7790_CLK_SCIFB1 7
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#define R8A7790_CLK_MSIOF1 8
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#define R8A7790_CLK_MSIOF3 15
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#define R8A7790_CLK_SCIFB2 16
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#define R8A7790_CLK_SYS_DMAC1 18
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#define R8A7790_CLK_SYS_DMAC0 19
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/* MSTP3 */
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#define R8A7790_CLK_IIC2 0
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#define R8A7790_CLK_TPU0 4
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#define R8A7790_CLK_MMCIF1 5
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#define R8A7790_CLK_SDHI3 11
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#define R8A7790_CLK_SDHI2 12
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#define R8A7790_CLK_SDHI1 13
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#define R8A7790_CLK_SDHI0 14
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#define R8A7790_CLK_MMCIF0 15
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#define R8A7790_CLK_IIC0 18
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#define R8A7790_CLK_IIC1 23
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#define R8A7790_CLK_SSUSB 28
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#define R8A7790_CLK_CMT1 29
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#define R8A7790_CLK_USBDMAC0 30
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#define R8A7790_CLK_USBDMAC1 31
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/* MSTP5 */
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#define R8A7790_CLK_THERMAL 22
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#define R8A7790_CLK_PWM 23
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/* MSTP7 */
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#define R8A7790_CLK_EHCI 3
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#define R8A7790_CLK_HSUSB 4
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#define R8A7790_CLK_HSCIF1 16
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#define R8A7790_CLK_HSCIF0 17
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#define R8A7790_CLK_SCIF1 20
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#define R8A7790_CLK_SCIF0 21
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#define R8A7790_CLK_DU2 22
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#define R8A7790_CLK_DU1 23
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#define R8A7790_CLK_DU0 24
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#define R8A7790_CLK_LVDS1 25
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#define R8A7790_CLK_LVDS0 26
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/* MSTP8 */
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#define R8A7790_CLK_VIN3 8
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#define R8A7790_CLK_VIN2 9
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#define R8A7790_CLK_VIN1 10
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#define R8A7790_CLK_VIN0 11
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#define R8A7790_CLK_ETHER 13
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#define R8A7790_CLK_SATA1 14
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#define R8A7790_CLK_SATA0 15
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/* MSTP9 */
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#define R8A7790_CLK_GPIO5 7
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#define R8A7790_CLK_GPIO4 8
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#define R8A7790_CLK_GPIO3 9
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#define R8A7790_CLK_GPIO2 10
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#define R8A7790_CLK_GPIO1 11
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#define R8A7790_CLK_GPIO0 12
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#define R8A7790_CLK_RCAN1 15
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#define R8A7790_CLK_RCAN0 16
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#define R8A7790_CLK_QSPI_MOD 17
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#define R8A7790_CLK_IICDVFS 26
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#define R8A7790_CLK_I2C3 28
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#define R8A7790_CLK_I2C2 29
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#define R8A7790_CLK_I2C1 30
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#define R8A7790_CLK_I2C0 31
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#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
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