dfc25e4503
Pull ARM SoC cleanups from Arnd Bergmann:
"These cleanup patches are mainly move stuff around and should all be
harmless. They are mainly split out so that other branches can be
based on top to avoid conflicts.
Notable changes are:
- We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used (Uwe Kleine-König)
- The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions (Kumar Gala)
- A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
- Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
- mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
- at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people)"
* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
ARM: hisi: select HAVE_ARM_SCU only for SMP
ARM: efm32: allow uncompress debug output
ARM: prima2: build reset code standalone
ARM: at91: add PWM clock
ARM: at91: move sam9261 SoC to common clk
ARM: at91: prepare common clk transition for sam9261 SoC
ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
ARM: at91: dt: Add at91sam9261 dt SoC support
ARM: at91: switch sam9rl to common clock framework
ARM: at91/dt: define main clk frequency of at91sam9rlek
ARM: at91/dt: define at91sam9rl clocks
ARM: at91: prepare common clk transition for sam9rl SoCs
ARM: at91: prepare sam9 dt boards transition to common clk
ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
ARM: at91: Add at91sam9rl DT SoC support
ARM: at91: prepare at91sam9rl DT transition
ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
...
140 lines
3.4 KiB
C
140 lines
3.4 KiB
C
/*
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* linux/arch/arm/mach-sa1100/time.c
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*
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* Copyright (C) 1998 Deborah Wallach.
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* Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
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*
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* 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
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* Rewritten: big cleanup, much simpler, better HZ accuracy.
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/timex.h>
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#include <linux/clockchips.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/time.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#define SA1100_CLOCK_FREQ 3686400
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#define SA1100_LATCH DIV_ROUND_CLOSEST(SA1100_CLOCK_FREQ, HZ)
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static u64 notrace sa1100_read_sched_clock(void)
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{
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return readl_relaxed(OSCR);
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}
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#define MIN_OSCR_DELTA 2
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static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *c = dev_id;
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/* Disarm the compare/match, signal the event. */
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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c->event_handler(c);
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return IRQ_HANDLED;
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}
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static int
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sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
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{
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unsigned long next, oscr;
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writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
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next = readl_relaxed(OSCR) + delta;
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writel_relaxed(next, OSMR0);
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oscr = readl_relaxed(OSCR);
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return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
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}
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static void
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sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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break;
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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}
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}
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#ifdef CONFIG_PM
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unsigned long osmr[4], oier;
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static void sa1100_timer_suspend(struct clock_event_device *cedev)
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{
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osmr[0] = readl_relaxed(OSMR0);
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osmr[1] = readl_relaxed(OSMR1);
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osmr[2] = readl_relaxed(OSMR2);
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osmr[3] = readl_relaxed(OSMR3);
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oier = readl_relaxed(OIER);
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}
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static void sa1100_timer_resume(struct clock_event_device *cedev)
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{
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writel_relaxed(0x0f, OSSR);
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writel_relaxed(osmr[0], OSMR0);
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writel_relaxed(osmr[1], OSMR1);
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writel_relaxed(osmr[2], OSMR2);
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writel_relaxed(osmr[3], OSMR3);
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writel_relaxed(oier, OIER);
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/*
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* OSMR0 is the system timer: make sure OSCR is sufficiently behind
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*/
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writel_relaxed(OSMR0 - SA1100_LATCH, OSCR);
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}
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#else
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#define sa1100_timer_suspend NULL
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#define sa1100_timer_resume NULL
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#endif
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static struct clock_event_device ckevt_sa1100_osmr0 = {
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.name = "osmr0",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_next_event = sa1100_osmr0_set_next_event,
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.set_mode = sa1100_osmr0_set_mode,
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.suspend = sa1100_timer_suspend,
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.resume = sa1100_timer_resume,
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};
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static struct irqaction sa1100_timer_irq = {
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.name = "ost0",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sa1100_ost0_interrupt,
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.dev_id = &ckevt_sa1100_osmr0,
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};
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void __init sa1100_timer_init(void)
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{
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writel_relaxed(0, OIER);
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writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
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sched_clock_register(sa1100_read_sched_clock, 32, 3686400);
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ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
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setup_irq(IRQ_OST0, &sa1100_timer_irq);
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clocksource_mmio_init(OSCR, "oscr", SA1100_CLOCK_FREQ, 200, 32,
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clocksource_mmio_readl_up);
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clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
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MIN_OSCR_DELTA * 2, 0x7fffffff);
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}
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