dfc25e4503
Pull ARM SoC cleanups from Arnd Bergmann:
"These cleanup patches are mainly move stuff around and should all be
harmless. They are mainly split out so that other branches can be
based on top to avoid conflicts.
Notable changes are:
- We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used (Uwe Kleine-König)
- The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions (Kumar Gala)
- A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
- Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
- mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
- at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people)"
* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
ARM: hisi: select HAVE_ARM_SCU only for SMP
ARM: efm32: allow uncompress debug output
ARM: prima2: build reset code standalone
ARM: at91: add PWM clock
ARM: at91: move sam9261 SoC to common clk
ARM: at91: prepare common clk transition for sam9261 SoC
ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
ARM: at91: dt: Add at91sam9261 dt SoC support
ARM: at91: switch sam9rl to common clock framework
ARM: at91/dt: define main clk frequency of at91sam9rlek
ARM: at91/dt: define at91sam9rl clocks
ARM: at91: prepare common clk transition for sam9rl SoCs
ARM: at91: prepare sam9 dt boards transition to common clk
ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
ARM: at91: Add at91sam9rl DT SoC support
ARM: at91: prepare at91sam9rl DT transition
ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
...
125 lines
3.2 KiB
C
125 lines
3.2 KiB
C
/* arch/arm/plat-s3c64xx/irq-pm.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Interrupt handling Power Management
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* NOTE: Code in this file is not used when booting with Device Tree support.
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*/
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#include <linux/kernel.h>
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#include <linux/syscore_ops.h>
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#include <linux/interrupt.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <mach/map.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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/* We handled all the IRQ types in this code, to save having to make several
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* small files to handle each different type separately. Having the EINT_GRP
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* code here shouldn't be as much bloat as the IRQ table space needed when
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* they are enabled. The added benefit is we ensure that these registers are
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* in the same state as we suspended.
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*/
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static struct sleep_save irq_save[] = {
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SAVE_ITEM(S3C64XX_PRIORITY),
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SAVE_ITEM(S3C64XX_EINT0CON0),
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SAVE_ITEM(S3C64XX_EINT0CON1),
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SAVE_ITEM(S3C64XX_EINT0FLTCON0),
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SAVE_ITEM(S3C64XX_EINT0FLTCON1),
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SAVE_ITEM(S3C64XX_EINT0FLTCON2),
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SAVE_ITEM(S3C64XX_EINT0FLTCON3),
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SAVE_ITEM(S3C64XX_EINT0MASK),
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};
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static struct irq_grp_save {
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u32 fltcon;
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u32 con;
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u32 mask;
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} eint_grp_save[5];
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#ifndef CONFIG_SERIAL_SAMSUNG_UARTS
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#define SERIAL_SAMSUNG_UARTS 0
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#else
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#define SERIAL_SAMSUNG_UARTS CONFIG_SERIAL_SAMSUNG_UARTS
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#endif
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static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS];
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static int s3c64xx_irq_pm_suspend(void)
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{
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struct irq_grp_save *grp = eint_grp_save;
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int i;
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S3C_PMDBG("%s: suspending IRQs\n", __func__);
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s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
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for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
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irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
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for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
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grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
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grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
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grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
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}
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return 0;
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}
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static void s3c64xx_irq_pm_resume(void)
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{
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struct irq_grp_save *grp = eint_grp_save;
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int i;
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S3C_PMDBG("%s: resuming IRQs\n", __func__);
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s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
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for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
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__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
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for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
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__raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
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__raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
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__raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
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}
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S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
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}
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static struct syscore_ops s3c64xx_irq_syscore_ops = {
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.suspend = s3c64xx_irq_pm_suspend,
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.resume = s3c64xx_irq_pm_resume,
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};
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static __init int s3c64xx_syscore_init(void)
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{
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/* Appropriate drivers (pinctrl, uart) handle this when using DT. */
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if (of_have_populated_dt())
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return 0;
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register_syscore_ops(&s3c64xx_irq_syscore_ops);
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return 0;
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}
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core_initcall(s3c64xx_syscore_init);
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