dddd564dbb
Pull clk updates from Stephen Boyd:
"This time we've got one core change to introduce a bulk clk_get API,
some new clk drivers and updates for old ones. The diff is pretty
spread out across a handful of different SoC clk drivers for Broadcom,
TI, Qualcomm, Renesas, Rockchip, Samsung, and Allwinner, mostly due to
the introduction of new drivers.
Core:
- New clk bulk get APIs
- Clk divider APIs gained the ability to consider a different parent
than the current one
New Drivers:
- Renesas r8a779{0,1,2,4} CPG/MSSR
- TI Keystone SCI firmware controlled clks and OMAP4 clkctrl
- Qualcomm IPQ8074 SoCs
- Cortina Systems Gemini (SL3516/CS3516)
- Rockchip rk3128 SoCs
- Allwinner A83T clk control units
- Broadcom Stingray SoCs
- CPU clks for Mediatek MT8173/MT2701/MT7623 SoCs
Removed Drivers:
- Old non-DT version of the Realview clk driver
Updates:
- Renesas Kconfig/Makefile cleanups
- Amlogic CEC EE clk support
- Improved Armada 7K/8K cp110 clk support
- Rockchip clk id exposing, critical clk markings
- Samsung converted to clk_hw registration APIs
- Fixes for Samsung exynos5420 audio clks
- USB2 clks for Hisilicon hi3798cv200 SoC and video/camera clks for
hi3660"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (147 commits)
clk: gemini: Read status before using the value
clk: scpi: error when clock fails to register
clk: at91: Add sama5d2 suspend/resume
gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K
clk: keystone: TI_SCI_PROTOCOL is needed for clk driver
clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL
clk: uniphier: provide NAND controller clock rate
clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
clk: Add Gemini SoC clock controller
clk: iproc: Remove __init marking on iproc_pll_clk_setup()
clk: bcm: Add clocks for Stingray SOC
dt-bindings: clk: Extend binding doc for Stingray SOC
clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work
clk: renesas: cpg-mssr: Use of_device_get_match_data() helper
clk: hi6220: add acpu clock
clk: zx296718: export I2S mux clocks
clk: imx7d: create clocks behind rawnand clock gate
clk: hi3660: Set PPLL2 to 2880M
...
96 lines
3.1 KiB
Plaintext
96 lines
3.1 KiB
Plaintext
* Marvell EBU GPIO controller
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Required properties:
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- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
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"marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
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"marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
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Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
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should be used for the Discovery MV78200.
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"marvel,armadaxp-gpio" should be used for all Armada XP SoCs
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(MV78230, MV78260, MV78460).
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"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
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SoCs (either from AP or CP), see
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Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
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and
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Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
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for specific details about the offset property.
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- reg: Address and length of the register set for the device. Only one
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entry is expected, except for the "marvell,armadaxp-gpio" variant
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for which two entries are expected: one for the general registers,
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one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
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- interrupts: The list of interrupts that are used for all the pins
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managed by this GPIO bank. There can be more than one interrupt
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(example: 1 interrupt per 8 pins on Armada XP, which means 4
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interrupts per bank of 32 GPIOs).
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. Should be two.
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The first cell is the GPIO number.
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The second cell is used to specify flags:
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bits[3:0] trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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- gpio-controller: marks the device node as a gpio controller
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- ngpios: number of GPIOs this controller has
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- #gpio-cells: Should be two. The first cell is the pin number. The
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second cell is reserved for flags, unused at the moment.
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Optional properties:
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In order to use the GPIO lines in PWM mode, some additional optional
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properties are required.
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- compatible: Must contain "marvell,armada-370-gpio"
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- reg: an additional register set is needed, for the GPIO Blink
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Counter on/off registers.
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- reg-names: Must contain an entry "pwm" corresponding to the
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additional register range needed for PWM operation.
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- #pwm-cells: Should be two. The first cell is the GPIO line number. The
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second cell is the period in nanoseconds.
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- clocks: Must be a phandle to the clock for the GPIO controller.
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Example:
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gpio0: gpio@d0018100 {
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compatible = "marvell,armadaxp-gpio";
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reg = <0xd0018100 0x40>,
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<0xd0018800 0x30>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <16>, <17>, <18>, <19>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,armada-370-gpio";
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reg = <0x18140 0x40>, <0x181c8 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <17>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>, <88>, <89>;
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clocks = <&coreclk 0>;
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};
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