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8 Commits

Author SHA1 Message Date
Dinh Nguyen
620f5e1cbf dts: Rename DW APB timer compatible strings 
"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the
DW APB timer, just fed by different clocks. Thus, deprecate both
"dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ian.campbell@citrix.com>
CC: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
CC: Jamie Iles <jamie@jamieiles.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Olof Johansson <olof@lixom.net>

v3:
- Split out a separate that cleans up the timer entries and clock information.
- Clearly states which binding is deprecated in the bindings doc.

v2:
- Deprecate the "dw-apb-timer-osc" and "dw-apb-timer-sp" but maintain
  backwards compatibility in the driver.
 2013-08-29 12:59:02 -07:00
Dinh Nguyen
a92b83af28 ARM: socfpga: dts: Add gate-clock bindings 
Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed
the peripherals.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>
Signed-off-by: Olof Johansson <olof@lixom.net>
 2013-06-11 16:35:00 -07:00
Dinh Nguyen
3d954cf151 ARM: socfpga: dts: Add ethernet bindings for SOCFPGA 
Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>

v2:
- Moved "disabled" status to dtsi file
Signed-off-by: Olof Johansson <olof@lixom.net>
 2013-06-11 16:34:57 -07:00
Dinh Nguyen
042000b003 ARM: socfpga: Add clock entries into device tree 
Adds the main PLL clock groups for SOCFPGA into device tree file
so that the clock framework to query the clock and clock rates
appropriately.

$cat /sys/kernel/debug/clk/clk_summary
   clock                        enable_cnt  prepare_cnt  rate
---------------------------------------------------------------------
 osc1                           2           2            25000000
    sdram_pll                   0           0            400000000
       s2f_usr2_clk             0           0            66666666
       ddr_dq_clk               0           0            200000000
       ddr_2x_dqs_clk           0           0            400000000
       ddr_dqs_clk              0           0            200000000
    periph_pll                  2           2            500000000
       s2f_usr1_clk             0           0            50000000
       per_base_clk             4           4            100000000
       per_nand_mmc_clk         0           0            25000000
       per_qsi_clk              0           0            250000000
       emac1_clk                1           1            125000000
       emac0_clk                0           0            125000000
    main_pll                    1           1            1600000000
       cfg_s2f_usr0_clk         0           0            100000000
       main_nand_sdmmc_clk      0           0            100000000
       main_qspi_clk            0           0            400000000
       dbg_base_clk             0           0            400000000
       mainclk                  0           0            400000000
       mpuclk                   1           1            800000000
          smp_twd               1           1            200000000

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
 2013-04-14 20:17:59 -07:00
Padmavathi Venna
0d8abbfd96 Arm: socfpga: pl330: Add #dma-cells for generic dma binding support 
This patch adds #dma-cells property to PL330 DMA controller nodes for
supporting generic dma dt bindings on SOCFPGA platform. #dma-channels
and #dma-requests are not required now but added in advance.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2013-03-11 22:01:57 +01:00
Dinh Nguyen
c2ad284412 arm: socfpga: Add new device tree source for actual socfpga HW 
Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
 2013-02-11 19:37:19 -08:00
Dinh Nguyen
9c4566a117 ARM: socfpga: Enable SMP for socfpga 
Enable SMP for the SOCFPGA platform.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2012-10-26 14:59:39 +02:00
Dinh Nguyen
66314223aa ARM: socfpga: initial support for Altera's SOCFPGA platform 
Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2012-07-19 10:39:00 +02:00