xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
413,874 Commits 2 Branches 0 Tags
e4d26f4b080f55e9577b45e6b51a04971eb459e9
Commit Graph

7 Commits

Author SHA1 Message Date
Ralf Baechle
7034228792 MIPS: Whitespace cleanup. 
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2013-02-01 10:00:22 +01:00
David Daney
595789a192 MIPS: Octeon: Add support for OCTEON II PCIe 
OCTEON II SOCs have a different PCIe implementation than is present in
OCTEON Plus.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2985/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2011-12-08 12:32:57 +00:00
Uwe Kleine-König
b595076a18 tree-wide: fix comment/printk typos 
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
 2010-11-01 15:38:34 -04:00
David Daney
b93b2abce4 MIPS: Octeon: Rewrite DMA mapping functions. 
All Octeon chips can support more than 4GB of RAM.  Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.

Enable the swiotlb code to handle the cases where a device cannot directly
do DMA.  This is a complete rewrite of the Octeon DMA mapping code.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1639/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-10-29 19:08:32 +01:00
David Daney
2b5987abaf MIPS: Octeon: Allow more than 3.75GB of memory with PCIe 
We reserve the 3.75GB - 4GB region of PCIe address space for device to
device transfers, making the corresponding physical memory under
direct mapping unavailable for DMA.

To allow for PCIe DMA to all physical memory we map this chunk of
physical memory with BAR1.  Because of the resulting discontinuity in
the mapping function, we remove a page of memory at each end of the
range so multi-page DMA buffers can never be allocated that span the
range.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1535/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-08-05 13:26:31 +01:00
David Daney
838c05705e MIPS: Octeon PCIe: Make hardware and software bus numbers match. 
Some SiliconImage PCIe SATA controlers are not detected when the bus
numbers differ.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2009-08-03 17:52:44 +01:00
David Daney
01a6221a6a MIPS: Reorganize Cavium OCTEON PCI support. 
Move the cavium PCI files to the arch/mips/pci directory.  Also cleanup
comment formatting and code layout.  Code from pci-common.c, was moved
into other files.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2009-07-03 15:45:29 +01:00