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6069 Commits

Author SHA1 Message Date
Leo Liu
dc9b6e934b drm/amdgpu: enable Renoir VCN firmware loading 
By adding new Renoir VCN firmware

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
a46e1716f3 drm/amdgpu: add sdma golden settings for renoir 
This patch adds sdma golden settings for renoir asic.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
33294eb8cb drm/amdgpu: add gfx golden settings for renoir (v2) 
This patch adds gfx golden settings for renoir real asic.

v2: update settings (Alex)

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
6a7a0bdbfa drm/amdgpu: add psp_v12_0 for renoir (v2) 
1. Add psp ip block
2. Use direct loading type by default and it can also config psp
   loading type.
3. Bypass sos fw loading and xgmi&ras interface

v2: drop TA loading

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
6b3ad3b2da drm/amdgpu: set rlc funcs for renoir 
add gfx_v9_0_rlc_funcs for renoir

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
e09ce48182 drm/amdgpu: add asic funcs for renoir 
add asic funcs for renoir, init soc15_asic_funcs

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
b1326bbc63 drm/amdgpu: enable dce virtual ip module for Renoir 
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Aaron Liu
0126abd4d1 drm/amdgpu: fix no interrupt issue for renoir emu 
In renoir's ih model, there's a change in mmIH_CHICKEN
register, that limits IH to use physical address directly.
Those chicken bits need to be programmed first.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
61bdb39c91 drm/amdgpu: add renoir pci id 
Add Renoir PCI id support.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
05e1f0e0ab drm/amdgpu: set ip blocks for renoir 
Enable ip blocks for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:50 -05:00
Huang Rui
2d49738ae1 drm/amdgpu: add sdma support for renoir 
Add renoir checks to appropriate places.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
1aafd447bc drm/amdgpu: add gfx support for renoir 
Add Renoir checks to gfx9 code.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
378d53898a drm/amdgpu: set fw load type for renoir 
This patch sets fw load type as direct for renoir for the moment.
Will switch to psp when psp is ready.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
8787ee0145 drm/amdgpu: add gmc v9 supports for renoir 
Add gfx memory controller support for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
080deab66d drm/amdgpu: add soc15 common ip block support for renoir 
This patch adds common ip support for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
b51a26a02a drm/amdgpu: add renoir support for gpu_info and ip block setting 
This patch adds renoir support for gpu_info firmware and ip block setting.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Huang Rui
1eee4228a5 drm/amdgpu: add renoir asic_type enum 
This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[].

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Pierre-Eric Pelloux-Prayer
62cfcb9e23 drm/amdgpu: fix gfx9 soft recovery 
The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail.

v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
a840159c82 drm/amdgpu: enable mmhub clock gating for Arcturus 
Init MC_MGCG/LS flag. Also apply to athub CG.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
cb15e8046d drm/amdgpu: add mmhub clock gating for Arcturus 
Add 2 mmhub instances CG

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
15e2f43a72 drm/amdgpu: increase CGCG gfx idle threshold for Arcturus 
Follow the hw spec, and no need to consider gfxoff on Arcturus

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:49 -05:00
Le Ma
f9da7c4384 drm/amdgpu: add GFX_CP_LS flag to Arcturus 
Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
    drm/amdgpu: enable gfx clock gating for Arcturus

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Tao Zhou
5212a3bdf0 drm/amdgpu: remove ras block's feature status info in sysfs 
feature mask info is enough for rocm tool,
"cat /sys/class/drm/card0/device/ras/features" will get the
info like this:

feature mask: 0x3ffb

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
bee7b51ac9 drm/amdgpu: split athub clock gating from mmhub 
Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic
not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
f7ee199528 drm/amdgpu: enable sdma clock gating for Arcturus 
Init sdma MGCG/LS flag

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
8dc7e07cff drm/amdgpu: add sdma clock gating for Arcturus 
Add ARCTURUS case in sdma set clockgating function

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
78864760c2 drm/amdgpu: support sdma clock gating for more instances 
Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
5d111f5b3a drm/amdgpu: enable hdp clock gating for Arcturus 
Init hdp MGCG/LS flag as Vega20

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
6acb87acef drm/amdgpu: add hdp clock gating for Arcturus 
Add hdp CGLS for Arcturus in set common clockgating function

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
6b76ce62bf drm/amdgpu: enable gfx clock gating for Arcturus 
Init gfx MGCG/LS and CGCG/LS flag.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Le Ma
f60481a945 drm/amdgpu: add gfx clock gating for Arcturus 
Add ARCTURUS case in gfx set clockgating function. No 3d clock on Arcturus.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Tao Zhou
145b03eb73 drm/amdgpu: create mmhub ras framework 
enable mmhub ras feature and create sysfs/debugfs node for mmhub

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Tao Zhou
9fb2d8de4a drm/amdgpu: support mmhub ras in amdgpu ras 
call mmhub ras query/inject in amdgpu ras

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Tao Zhou
3d093da098 drm/amdgpu: add amdgpu_mmhub_funcs definition 
add amdgpu_mmhub_funcs definition and initialize it,
prepare for mmhub ras enablement

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Tao Zhou
44494f96ba drm/amdgpu: add sub block parameter in ras inject command 
ras sub block index could be passed from shell command

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Guchun Chen
a2b459947b drm/amdgpu: add check to avoid array bound issue 
Sub_block_index can be passed from user level, so
add one check before accessing the array first to
prevent array index out of bound problem.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:48 -05:00
Alex Deucher
2605172032 drm/amdgpu: add navi14 PCI ID 
Add the navi14 PCI device id.

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Michel Dänzer
965ebe3d5d drm/amdgpu: Update pitch on page flips without DC as well 
DC already handles this correctly since amdgpu minor version 31. Bump
the minor version again so that xf86-video-amdgpu can take advantage of
this working without DC as well now.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
65872e59d6 drm/amdgpu: enable vcn clock gating for navi12 
enables vcn medium grained clock gating

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
ca51678db4 drm/amdgpu: enable athub clock gating for navi12 
enables athub medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
89b8d6da24 drm/amdgpu/athub2: set clock gating for navi12 
add navi12 define

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
fbe0bc5794 drm/amdgpu: enable ih clock gating for navi12 
enables ih clock gating

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
8b797b3d30 drm/amdgpu: enable mmhub clock gating for navi12 
enables mmhub medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
cf5a95e5b8 drm/amdgpu/mmhub2: set clock gating for navi12 
add navi12 define

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
358ab97f53 drm/amdgpu: enable sdma clock gating for navi12 
enables sdma medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
e2f9726ee9 drm/amdgpu/sdma5: set sdma clock gating for navi12 
add navi12 define

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
5211c37a34 drm/amdgpu: enable hdp clock gating for navi12 
enables hdp medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
dca009e71c drm/amdgpu: enable gfx clock gatings for navi12 
enables following gfx clock gating features:

- medium grained clock gating
- medium grained light sleep
- coarse grained clock gating
- cp memory light sleep
- rlc memory light sleep

CGLS (Coarse Grained Light Sleep) will break s3, so don't enable it.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Marek Olšák
05677c958a Revert "drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)" 
This reverts commit 9ed2c993d7.

SET_CONFIG_REG writes to memory if register shadowing is enabled,
causing a VM fault.

NGG streamout is unstable anyway, so all UMDs should use legacy
streamout. I think Mesa is the only driver using NGG streamout.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Dave Airlie
e7f7287bf5 Merge tag 'drm-next-5.4-2019-08-09' of git://people.freedesktop.org/~agd5f/linux into drm-next 
drm-next-5.4-2019-08-09:

Same as drm-next-5.4-2019-08-06, but with the
readq/writeq stuff fixed and 5.3-rc3 backmerged.

amdgpu:
- Add navi14 support
- Add navi12 support
- Add Arcturus support
- Enable mclk DPM for Navi
- Misc DC display fixes
- Add perfmon support for DF
- Add scatter/gather display support for Raven
- Improve SMU handling for GPU reset
- RAS support for GFX
- Drop last of drmP.h
- Add support for wiping memory on buffer release
- Allow cursor async updates for fb swaps
- Misc fixes and cleanups

amdkfd:
- Add navi14 support
- Add navi12 support
- Add Arcturus support
- CWSR trap handlers updates for gfx9, 10
- Drop last of drmP.h
- Update MAINTAINERS

radeon:
- Misc fixes and cleanups
- Make kexec more reliable by tearing down the GPU

ttm:
- Add release_notify callback

uapi:
- Add wipe memory on release flag for buffer creation

Signed-off-by: Dave Airlie <airlied@redhat.com>
[airlied: resolved conflicts with ttm resv moving]
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190809184807.3381-1-alexander.deucher@amd.com
 2019-08-12 14:20:21 +10:00