4 Commits

Author	SHA1	Message	Date
Andy Gross	4d9b766bfe	arm: dts: qcom: Add TCSR support for IPQ8064 ... This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>	2015-04-03 13:33:44 -07:00
Stephen Boyd	bb901bd659	ARM: dts: qcom: Correct IPQ8064 tlmm interrupt ... The interrupt is 16, not 32 (which it would be if we include PPIs in the count of interrupts). Cc: Andy Gross <agross@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Tested-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>	2015-01-19 12:11:41 -06:00
Kumar Gala	e512448f6e	ARM: dts: qcom: Add SATA support on IPQ8064/AP148 ... Add SATA PHY and SATA AHCI controller nodes to device tree to enable generic ahci support on the IPQ8064/AP148 board. Signed-off-by: Kumar Gala <galak@codeaurora.org>	2014-10-16 02:44:47 -05:00
Kumar Gala	68de308b1c	ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees ... Add basic IPQ8064 SoC include device tree and support for basic booting on the AP148 Reference board with support for UART, I2C, and SPI. Signed-off-by: Kumar Gala <galak@codeaurora.org>	2014-08-21 11:43:34 -05:00