Commit Graph

181 Commits

Author SHA1 Message Date
Greg Kroah-Hartman
27b36ba7c2 Merge 5.10.152 into android12-5.10-lts
Changes in 5.10.152
	ocfs2: clear dinode links count in case of error
	ocfs2: fix BUG when iput after ocfs2_mknod fails
	selinux: enable use of both GFP_KERNEL and GFP_ATOMIC in convert_context()
	cpufreq: qcom: fix writes in read-only memory region
	i2c: qcom-cci: Fix ordering of pm_runtime_xx and i2c_add_adapter
	x86/microcode/AMD: Apply the patch early on every logical thread
	hwmon/coretemp: Handle large core ID value
	ata: ahci-imx: Fix MODULE_ALIAS
	ata: ahci: Match EM_MAX_SLOTS with SATA_PMP_MAX_PORTS
	cpufreq: qcom: fix memory leak in error path
	kvm: Add support for arch compat vm ioctls
	KVM: arm64: vgic: Fix exit condition in scan_its_table()
	media: mceusb: set timeout to at least timeout provided
	media: venus: dec: Handle the case where find_format fails
	block: wbt: Remove unnecessary invoking of wbt_update_limits in wbt_init
	blk-wbt: call rq_qos_add() after wb_normal is initialized
	arm64: errata: Remove AES hwcap for COMPAT tasks
	r8152: add PID for the Lenovo OneLink+ Dock
	btrfs: fix processing of delayed data refs during backref walking
	btrfs: fix processing of delayed tree block refs during backref walking
	ACPI: extlog: Handle multiple records
	tipc: Fix recognition of trial period
	tipc: fix an information leak in tipc_topsrv_kern_subscr
	i40e: Fix DMA mappings leak
	HID: magicmouse: Do not set BTN_MOUSE on double report
	sfc: Change VF mac via PF as first preference if available.
	net/atm: fix proc_mpc_write incorrect return value
	net: phy: dp83867: Extend RX strap quirk for SGMII mode
	cifs: Fix xid leak in cifs_copy_file_range()
	cifs: Fix xid leak in cifs_flock()
	cifs: Fix xid leak in cifs_ses_add_channel()
	net: hsr: avoid possible NULL deref in skb_clone()
	ionic: catch NULL pointer issue on reconfig
	nvme-hwmon: rework to avoid devm allocation
	nvme-hwmon: Return error code when registration fails
	nvme-hwmon: consistently ignore errors from nvme_hwmon_init
	nvme-hwmon: kmalloc the NVME SMART log buffer
	net: sched: cake: fix null pointer access issue when cake_init() fails
	net: sched: delete duplicate cleanup of backlog and qlen
	net: sched: sfb: fix null pointer access issue when sfb_init() fails
	sfc: include vport_id in filter spec hash and equal()
	net: hns: fix possible memory leak in hnae_ae_register()
	net: sched: fix race condition in qdisc_graft()
	net: phy: dp83822: disable MDI crossover status change interrupt
	iommu/vt-d: Allow NVS regions in arch_rmrr_sanity_check()
	iommu/vt-d: Clean up si_domain in the init_dmars() error path
	drm/virtio: Use appropriate atomic state in virtio_gpu_plane_cleanup_fb()
	dmaengine: mxs-dma: Remove the unused .id_table
	dmaengine: mxs: use platform_driver_register
	tracing: Simplify conditional compilation code in tracing_set_tracer()
	tracing: Do not free snapshot if tracer is on cmdline
	xen: assume XENFEAT_gnttab_map_avail_bits being set for pv guests
	xen/gntdev: Accommodate VMA splitting
	mmc: sdhci-tegra: Use actual clock rate for SW tuning correction
	riscv: Add machine name to kernel boot log and stack dump output
	riscv: always honor the CONFIG_CMDLINE_FORCE when parsing dtb
	perf pmu: Validate raw event with sysfs exported format bits
	perf: Skip and warn on unknown format 'configN' attrs
	fcntl: make F_GETOWN(EX) return 0 on dead owner task
	fcntl: fix potential deadlocks for &fown_struct.lock
	arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region
	arm64: topology: move store_cpu_topology() to shared code
	riscv: topology: fix default topology reporting
	perf/x86/intel/pt: Relax address filter validation
	hv_netvsc: Fix race between VF offering and VF association message from host
	ACPI: video: Force backlight native for more TongFang devices
	x86/Kconfig: Drop check for -mabi=ms for CONFIG_EFI_STUB
	Makefile.debug: re-enable debug info for .S files
	mmc: core: Add SD card quirk for broken discard
	blk-wbt: fix that 'rwb->wc' is always set to 1 in wbt_init()
	mm: /proc/pid/smaps_rollup: fix no vma's null-deref
	udp: Update reuse->has_conns under reuseport_lock.
	Linux 5.10.152

Change-Id: I2c75b6fd3ae205968bcc3133ebf71b82ff2a19b6
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2022-11-21 15:46:22 +00:00
James Morse
51b96ecaed arm64: errata: Remove AES hwcap for COMPAT tasks
commit 44b3834b2eed595af07021b1c64e6f9bc396398b upstream.

Cortex-A57 and Cortex-A72 have an erratum where an interrupt that
occurs between a pair of AES instructions in aarch32 mode may corrupt
the ELR. The task will subsequently produce the wrong AES result.

The AES instructions are part of the cryptographic extensions, which are
optional. User-space software will detect the support for these
instructions from the hwcaps. If the platform doesn't support these
instructions a software implementation should be used.

Remove the hwcap bits on affected parts to indicate user-space should
not use the AES instructions.

Acked-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220714161523.279570-3-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
[florian: removed arch/arm64/tools/cpucaps and fixup cpufeature.c]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-10-30 09:41:16 +01:00
Greg Kroah-Hartman
3dbfa90b61 Merge 5.10.143 into android12-5.10-lts
Changes in 5.10.143
	NFSD: Fix verifier returned in stable WRITEs
	xen-blkfront: Cache feature_persistent value before advertisement
	tty: n_gsm: initialize more members at gsm_alloc_mux()
	tty: n_gsm: avoid call of sleeping functions from atomic context
	efi: libstub: Disable struct randomization
	efi: capsule-loader: Fix use-after-free in efi_capsule_write
	wifi: iwlegacy: 4965: corrected fix for potential off-by-one overflow in il4965_rs_fill_link_cmd()
	fs: only do a memory barrier for the first set_buffer_uptodate()
	Revert "mm: kmemleak: take a full lowmem check in kmemleak_*_phys()"
	scsi: qla2xxx: Disable ATIO interrupt coalesce for quad port ISP27XX
	scsi: megaraid_sas: Fix double kfree()
	drm/gem: Fix GEM handle release errors
	drm/amdgpu: Move psp_xgmi_terminate call from amdgpu_xgmi_remove_device to psp_hw_fini
	drm/amdgpu: Check num_gfx_rings for gfx v9_0 rb setup.
	drm/radeon: add a force flush to delay work when radeon
	parisc: ccio-dma: Handle kmalloc failure in ccio_init_resources()
	parisc: Add runtime check to prevent PA2.0 kernels on PA1.x machines
	arm64: cacheinfo: Fix incorrect assignment of signed error value to unsigned fw_level
	net/core/skbuff: Check the return value of skb_copy_bits()
	fbdev: chipsfb: Add missing pci_disable_device() in chipsfb_pci_init()
	drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly
	ALSA: emu10k1: Fix out of bounds access in snd_emu10k1_pcm_channel_alloc()
	ALSA: aloop: Fix random zeros in capture data when using jiffies timer
	ALSA: usb-audio: Fix an out-of-bounds bug in __snd_usb_parse_audio_interface()
	kprobes: Prohibit probes in gate area
	debugfs: add debugfs_lookup_and_remove()
	nvmet: fix a use-after-free
	drm/i915: Implement WaEdpLinkRateDataReload
	scsi: mpt3sas: Fix use-after-free warning
	scsi: lpfc: Add missing destroy_workqueue() in error path
	cgroup: Elide write-locking threadgroup_rwsem when updating csses on an empty subtree
	cgroup: Fix threadgroup_rwsem <-> cpus_read_lock() deadlock
	cifs: remove useless parameter 'is_fsctl' from SMB2_ioctl()
	smb3: missing inode locks in punch hole
	ARM: dts: imx6qdl-kontron-samx6i: remove duplicated node
	regulator: core: Clean up on enable failure
	tee: fix compiler warning in tee_shm_register()
	RDMA/cma: Fix arguments order in net device validation
	soc: brcmstb: pm-arm: Fix refcount leak and __iomem leak bugs
	RDMA/hns: Fix supported page size
	RDMA/hns: Fix wrong fixed value of qp->rq.wqe_shift
	ARM: dts: at91: sama5d27_wlsom1: specify proper regulator output ranges
	ARM: dts: at91: sama5d2_icp: specify proper regulator output ranges
	ARM: dts: at91: sama5d27_wlsom1: don't keep ldo2 enabled all the time
	ARM: dts: at91: sama5d2_icp: don't keep vdd_other enabled all the time
	netfilter: br_netfilter: Drop dst references before setting.
	netfilter: nf_tables: clean up hook list when offload flags check fails
	netfilter: nf_conntrack_irc: Fix forged IP logic
	ALSA: usb-audio: Inform the delayed registration more properly
	ALSA: usb-audio: Register card again for iface over delayed_register option
	rxrpc: Fix an insufficiently large sglist in rxkad_verify_packet_2()
	afs: Use the operation issue time instead of the reply time for callbacks
	sch_sfb: Don't assume the skb is still around after enqueueing to child
	tipc: fix shift wrapping bug in map_get()
	ice: use bitmap_free instead of devm_kfree
	i40e: Fix kernel crash during module removal
	xen-netback: only remove 'hotplug-status' when the vif is actually destroyed
	RDMA/siw: Pass a pointer to virt_to_page()
	ipv6: sr: fix out-of-bounds read when setting HMAC data.
	IB/core: Fix a nested dead lock as part of ODP flow
	RDMA/mlx5: Set local port to one when accessing counters
	nvme-tcp: fix UAF when detecting digest errors
	nvme-tcp: fix regression that causes sporadic requests to time out
	tcp: fix early ETIMEDOUT after spurious non-SACK RTO
	sch_sfb: Also store skb len before calling child enqueue
	ASoC: mchp-spdiftx: remove references to mchp_i2s_caps
	ASoC: mchp-spdiftx: Fix clang -Wbitfield-constant-conversion
	MIPS: loongson32: ls1c: Fix hang during startup
	swiotlb: avoid potential left shift overflow
	iommu/amd: use full 64-bit value in build_completion_wait()
	hwmon: (mr75203) fix VM sensor allocation when "intel,vm-map" not defined
	hwmon: (mr75203) update pvt->v_num and vm_num to the actual number of used sensors
	hwmon: (mr75203) fix voltage equation for negative source input
	hwmon: (mr75203) fix multi-channel voltage reading
	hwmon: (mr75203) enable polling for all VM channels
	arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly
	Linux 5.10.143

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ia1bc1b76bcad0e2cb3b27d1a37278b1d24c6b90d
2022-09-22 14:38:08 +02:00
Ionela Voinescu
71d3adbb28 arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly
commit e89d120c4b720e232cc6a94f0fcbd59c15d41489 upstream.

The AMU counter AMEVCNTR01 (constant counter) should increment at the same
rate as the system counter. On affected Cortex-A510 cores, AMEVCNTR01
increments incorrectly giving a significantly higher output value. This
results in inaccurate task scheduler utilization tracking and incorrect
feedback on CPU frequency.

Work around this problem by returning 0 when reading the affected counter
in key locations that results in disabling all users of this counter from
using it either for frequency invariance or as FFH reference counter. This
effect is the same to firmware disabling affected counters.

Details on how the two features are affected by this erratum:

 - AMU counters will not be used for frequency invariance for affected
   CPUs and CPUs in the same cpufreq policy. AMUs can still be used for
   frequency invariance for unaffected CPUs in the system. Although
   unlikely, if no alternative method can be found to support frequency
   invariance for affected CPUs (cpufreq based or solution based on
   platform counters) frequency invariance will be disabled. Please check
   the chapter on frequency invariance at
   Documentation/scheduler/sched-capacity.rst for details of its effect.

 - Given that FFH can be used to fetch either the core or constant counter
   values, restrictions are lifted regarding any of these counters
   returning a valid (!0) value. Therefore FFH is considered supported
   if there is a least one CPU that support AMUs, independent of any
   counters being disabled or affected by this erratum. Clarifying
   comments are now added to the cpc_ffh_supported(), cpu_read_constcnt()
   and cpu_read_corecnt() functions.

The above is achieved through adding a new erratum: ARM64_ERRATUM_2457168.

Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220819103050.24211-1-ionela.voinescu@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-09-15 11:32:06 +02:00
Greg Kroah-Hartman
5939035887 Merge 5.10.140 into android12-5.10-lts
Changes in 5.10.140
	audit: fix potential double free on error path from fsnotify_add_inode_mark
	parisc: Fix exception handler for fldw and fstw instructions
	kernel/sys_ni: add compat entry for fadvise64_64
	pinctrl: amd: Don't save/restore interrupt status and wake status bits
	xfs: prevent a WARN_ONCE() in xfs_ioc_attr_list()
	xfs: reject crazy array sizes being fed to XFS_IOC_GETBMAP*
	fs: remove __sync_filesystem
	vfs: make sync_filesystem return errors from ->sync_fs
	xfs: return errors in xfs_fs_sync_fs
	xfs: only bother with sync_filesystem during readonly remount
	kernel/sched: Remove dl_boosted flag comment
	xfrm: fix refcount leak in __xfrm_policy_check()
	xfrm: clone missing x->lastused in xfrm_do_migrate
	af_key: Do not call xfrm_probe_algs in parallel
	xfrm: policy: fix metadata dst->dev xmit null pointer dereference
	NFS: Don't allocate nfs_fattr on the stack in __nfs42_ssc_open()
	NFSv4.2 fix problems with __nfs42_ssc_open
	SUNRPC: RPC level errors should set task->tk_rpc_status
	mm/huge_memory.c: use helper function migration_entry_to_page()
	mm/smaps: don't access young/dirty bit if pte unpresent
	rose: check NULL rose_loopback_neigh->loopback
	nfc: pn533: Fix use-after-free bugs caused by pn532_cmd_timeout
	ice: xsk: Force rings to be sized to power of 2
	ice: xsk: prohibit usage of non-balanced queue id
	net/mlx5e: Properly disable vlan strip on non-UL reps
	net: ipa: don't assume SMEM is page-aligned
	net: moxa: get rid of asymmetry in DMA mapping/unmapping
	bonding: 802.3ad: fix no transmission of LACPDUs
	net: ipvtap - add __init/__exit annotations to module init/exit funcs
	netfilter: ebtables: reject blobs that don't provide all entry points
	bnxt_en: fix NQ resource accounting during vf creation on 57500 chips
	netfilter: nft_payload: report ERANGE for too long offset and length
	netfilter: nft_payload: do not truncate csum_offset and csum_type
	netfilter: nf_tables: do not leave chain stats enabled on error
	netfilter: nft_osf: restrict osf to ipv4, ipv6 and inet families
	netfilter: nft_tunnel: restrict it to netdev family
	netfilter: nftables: remove redundant assignment of variable err
	netfilter: nf_tables: consolidate rule verdict trace call
	netfilter: nft_cmp: optimize comparison for 16-bytes
	netfilter: bitwise: improve error goto labels
	netfilter: nf_tables: upfront validation of data via nft_data_init()
	netfilter: nf_tables: disallow jump to implicit chain from set element
	netfilter: nf_tables: disallow binding to already bound chain
	tcp: tweak len/truesize ratio for coalesce candidates
	net: Fix data-races around sysctl_[rw]mem(_offset)?.
	net: Fix data-races around sysctl_[rw]mem_(max|default).
	net: Fix data-races around weight_p and dev_weight_[rt]x_bias.
	net: Fix data-races around netdev_max_backlog.
	net: Fix data-races around netdev_tstamp_prequeue.
	ratelimit: Fix data-races in ___ratelimit().
	bpf: Folding omem_charge() into sk_storage_charge()
	net: Fix data-races around sysctl_optmem_max.
	net: Fix a data-race around sysctl_tstamp_allow_data.
	net: Fix a data-race around sysctl_net_busy_poll.
	net: Fix a data-race around sysctl_net_busy_read.
	net: Fix a data-race around netdev_budget.
	net: Fix a data-race around netdev_budget_usecs.
	net: Fix data-races around sysctl_fb_tunnels_only_for_init_net.
	net: Fix data-races around sysctl_devconf_inherit_init_net.
	net: Fix a data-race around sysctl_somaxconn.
	ixgbe: stop resetting SYSTIME in ixgbe_ptp_start_cyclecounter
	rxrpc: Fix locking in rxrpc's sendmsg
	ionic: fix up issues with handling EAGAIN on FW cmds
	btrfs: fix silent failure when deleting root reference
	btrfs: replace: drop assert for suspended replace
	btrfs: add info when mount fails due to stale replace target
	btrfs: check if root is readonly while setting security xattr
	perf/x86/lbr: Enable the branch type for the Arch LBR by default
	x86/unwind/orc: Unwind ftrace trampolines with correct ORC entry
	x86/bugs: Add "unknown" reporting for MMIO Stale Data
	loop: Check for overflow while configuring loop
	asm-generic: sections: refactor memory_intersects
	s390: fix double free of GS and RI CBs on fork() failure
	ACPI: processor: Remove freq Qos request for all CPUs
	xen/privcmd: fix error exit of privcmd_ioctl_dm_op()
	mm/hugetlb: fix hugetlb not supporting softdirty tracking
	Revert "md-raid: destroy the bitmap after destroying the thread"
	md: call __md_stop_writes in md_stop
	arm64: Fix match_list for erratum 1286807 on Arm Cortex-A76
	Documentation/ABI: Mention retbleed vulnerability info file for sysfs
	blk-mq: fix io hung due to missing commit_rqs
	perf python: Fix build when PYTHON_CONFIG is user supplied
	perf/x86/intel/uncore: Fix broken read_counter() for SNB IMC PMU
	scsi: ufs: core: Enable link lost interrupt
	scsi: storvsc: Remove WQ_MEM_RECLAIM from storvsc_error_wq
	bpf: Don't use tnum_range on array range checking for poke descriptors
	Linux 5.10.140

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I29f4b4af2a584dc2f2789aac613583603002464a
2022-08-31 18:52:48 +02:00
Zenghui Yu
1896232619 arm64: Fix match_list for erratum 1286807 on Arm Cortex-A76
commit 5e1e087457c94ad7fafbe1cf6f774c6999ee29d4 upstream.

Since commit 51f559d66527 ("arm64: Enable repeat tlbi workaround on KRYO4XX
gold CPUs"), we failed to detect erratum 1286807 on Cortex-A76 because its
entry in arm64_repeat_tlbi_list[] was accidently corrupted by this commit.

Fix this issue by creating a separate entry for Kryo4xx Gold.

Fixes: 51f559d66527 ("arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs")
Cc: Shreyas K K <quic_shrekk@quicinc.com>
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220809043848.969-1-yuzenghui@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-08-31 17:15:23 +02:00
Greg Kroah-Hartman
43ca8e1dfb Merge 5.10.118 into android12-5.10-lts
Changes in 5.10.118
	usb: gadget: fix race when gadget driver register via ioctl
	io_uring: always grab file table for deferred statx
	floppy: use a statically allocated error counter
	Revert "drm/i915/opregion: check port number bounds for SWSCI display power state"
	igc: Remove _I_PHY_ID checking
	igc: Remove phy->type checking
	igc: Update I226_K device ID
	rtc: fix use-after-free on device removal
	rtc: pcf2127: fix bug when reading alarm registers
	um: Cleanup syscall_handler_t definition/cast, fix warning
	Input: add bounds checking to input_set_capability()
	Input: stmfts - fix reference leak in stmfts_input_open
	nvme-pci: add quirks for Samsung X5 SSDs
	gfs2: Disable page faults during lockless buffered reads
	rtc: sun6i: Fix time overflow handling
	crypto: stm32 - fix reference leak in stm32_crc_remove
	crypto: x86/chacha20 - Avoid spurious jumps to other functions
	ALSA: hda/realtek: Enable headset mic on Lenovo P360
	s390/pci: improve zpci_dev reference counting
	vhost_vdpa: don't setup irq offloading when irq_num < 0
	tools/virtio: compile with -pthread
	nvme-multipath: fix hang when disk goes live over reconnect
	rtc: mc146818-lib: Fix the AltCentury for AMD platforms
	fs: fix an infinite loop in iomap_fiemap
	MIPS: lantiq: check the return value of kzalloc()
	drbd: remove usage of list iterator variable after loop
	platform/chrome: cros_ec_debugfs: detach log reader wq from devm
	ARM: 9191/1: arm/stacktrace, kasan: Silence KASAN warnings in unwind_frame()
	nilfs2: fix lockdep warnings in page operations for btree nodes
	nilfs2: fix lockdep warnings during disk space reclamation
	Revert "swiotlb: fix info leak with DMA_FROM_DEVICE"
	Reinstate some of "swiotlb: rework "fix info leak with DMA_FROM_DEVICE""
	ALSA: usb-audio: Restore Rane SL-1 quirk
	ALSA: wavefront: Proper check of get_user() error
	ALSA: hda/realtek: Add quirk for TongFang devices with pop noise
	perf: Fix sys_perf_event_open() race against self
	selinux: fix bad cleanup on error in hashtab_duplicate()
	Fix double fget() in vhost_net_set_backend()
	PCI/PM: Avoid putting Elo i2 PCIe Ports in D3cold
	KVM: x86/mmu: Update number of zapped pages even if page list is stable
	arm64: paravirt: Use RCU read locks to guard stolen_time
	arm64: mte: Ensure the cleared tags are visible before setting the PTE
	crypto: qcom-rng - fix infinite loop on requests not multiple of WORD_SZ
	libceph: fix potential use-after-free on linger ping and resends
	drm/dp/mst: fix a possible memory leak in fetch_monitor_name()
	dma-buf: fix use of DMA_BUF_SET_NAME_{A,B} in userspace
	ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi
	pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
	ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group
	net: ipa: record proper RX transaction count
	net: macb: Increment rx bd head after allocating skb and buffer
	net: evaluate net.ipvX.conf.all.disable_policy and disable_xfrm
	xfrm: Add possibility to set the default to block if we have no policy
	net: xfrm: fix shift-out-of-bounce
	xfrm: make user policy API complete
	xfrm: notify default policy on update
	xfrm: fix dflt policy check when there is no policy configured
	xfrm: rework default policy structure
	xfrm: fix "disable_policy" flag use when arriving from different devices
	net/sched: act_pedit: sanitize shift argument before usage
	net: systemport: Fix an error handling path in bcm_sysport_probe()
	net: vmxnet3: fix possible use-after-free bugs in vmxnet3_rq_alloc_rx_buf()
	net: vmxnet3: fix possible NULL pointer dereference in vmxnet3_rq_cleanup()
	ice: fix possible under reporting of ethtool Tx and Rx statistics
	clk: at91: generated: consider range when calculating best rate
	net/qla3xxx: Fix a test in ql_reset_work()
	NFC: nci: fix sleep in atomic context bugs caused by nci_skb_alloc
	net/mlx5e: Properly block LRO when XDP is enabled
	net: af_key: add check for pfkey_broadcast in function pfkey_process
	ARM: 9196/1: spectre-bhb: enable for Cortex-A15
	ARM: 9197/1: spectre-bhb: fix loop8 sequence for Thumb2
	igb: skip phy status check where unavailable
	net: bridge: Clear offload_fwd_mark when passing frame up bridge interface.
	riscv: dts: sifive: fu540-c000: align dma node name with dtschema
	gpio: gpio-vf610: do not touch other bits when set the target bit
	gpio: mvebu/pwm: Refuse requests with inverted polarity
	perf bench numa: Address compiler error on s390
	scsi: qla2xxx: Fix missed DMA unmap for aborted commands
	mac80211: fix rx reordering with non explicit / psmp ack policy
	nl80211: validate S1G channel width
	selftests: add ping test with ping_group_range tuned
	nl80211: fix locking in nl80211_set_tx_bitrate_mask()
	ethernet: tulip: fix missing pci_disable_device() on error in tulip_init_one()
	net: stmmac: fix missing pci_disable_device() on error in stmmac_pci_probe()
	net: atlantic: fix "frag[0] not initialized"
	net: atlantic: reduce scope of is_rsc_complete
	net: atlantic: add check for MAX_SKB_FRAGS
	net: atlantic: verify hw_head_ lies within TX buffer ring
	arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs
	Input: ili210x - fix reset timing
	dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
	module: treat exit sections the same as init sections when !CONFIG_MODULE_UNLOAD
	i2c: mt7621: fix missing clk_disable_unprepare() on error in mtk_i2c_probe()
	afs: Fix afs_getattr() to refetch file status if callback break occurred
	include/uapi/linux/xfrm.h: Fix XFRM_MSG_MAPPING ABI breakage
	module: check for exit sections in layout_sections() instead of module_init_section()
	Linux 5.10.118

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I7093fab7ea7d43c42962f2d7fe799df255049a17
2022-06-06 16:37:12 +02:00
Shreyas K K
a698bf1f72 arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs
[ Upstream commit 51f559d66527e238f9a5f82027bff499784d4eac ]

Add KRYO4XX gold/big cores to the list of CPUs that need the
repeat TLBI workaround. Apply this to the affected
KRYO4XX cores (rcpe to rfpe).

The variant and revision bits are implementation defined and are
different from the their Cortex CPU counterparts on which they are
based on, i.e., (r0p0 to r3p0) is equivalent to (rcpe to rfpe).

Signed-off-by: Shreyas K K <quic_shrekk@quicinc.com>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Link: https://lore.kernel.org/r/20220512110134.12179-1-quic_shrekk@quicinc.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-05-25 09:18:01 +02:00
James Morse
11bed3edbd UPSTREAM: arm64: Mitigate spectre style branch history side channels
commit 558c303c9734af5a813739cd284879227f7297d2 upstream.

Speculation attacks against some high-performance processors can
make use of branch history to influence future speculation.
When taking an exception from user-space, a sequence of branches
or a firmware call overwrites or invalidates the branch history.

The sequence of branches is added to the vectors, and should appear
before the first indirect branch. For systems using KPTI the sequence
is added to the kpti trampoline where it has a free register as the exit
from the trampoline is via a 'ret'. For systems not using KPTI, the same
register tricks are used to free up a register in the vectors.

For the firmware call, arch-workaround-3 clobbers 4 registers, so
there is no choice but to save them to the EL1 stack. This only happens
for entry from EL0, so if we take an exception due to the stack access,
it will not become re-entrant.

For KVM, the existing branch-predictor-hardening vectors are used.
When a spectre version of these vectors is in use, the firmware call
is sufficient to mitigate against Spectre-BHB. For the non-spectre
versions, the sequence of branches is added to the indirect vector.

Bug: 215557547
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Change-Id: I7d1f5a9767d1dbc9e6ef363ca3bf7bffe91c402c
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2022-03-18 09:57:27 +01:00
James Morse
e192c8baa6 arm64: Mitigate spectre style branch history side channels
commit 558c303c9734af5a813739cd284879227f7297d2 upstream.

Speculation attacks against some high-performance processors can
make use of branch history to influence future speculation.
When taking an exception from user-space, a sequence of branches
or a firmware call overwrites or invalidates the branch history.

The sequence of branches is added to the vectors, and should appear
before the first indirect branch. For systems using KPTI the sequence
is added to the kpti trampoline where it has a free register as the exit
from the trampoline is via a 'ret'. For systems not using KPTI, the same
register tricks are used to free up a register in the vectors.

For the firmware call, arch-workaround-3 clobbers 4 registers, so
there is no choice but to save them to the EL1 stack. This only happens
for entry from EL0, so if we take an exception due to the stack access,
it will not become re-entrant.

For KVM, the existing branch-predictor-hardening vectors are used.
When a spectre version of these vectors is in use, the firmware call
is sufficient to mitigate against Spectre-BHB. For the non-spectre
versions, the sequence of branches is added to the indirect vector.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
[ modified for stable, removed bitmap of mitigations,  use kvm template
  infrastructure ]
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-11 12:11:53 +01:00
Suzuki K Poulose
a512242e66 BACKPORT: arm64: errata: Add workaround for TSB flush failures
Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers
from errata, where a TSB (trace synchronization barrier)
fails to flush the trace data completely, when executed from
a trace prohibited region. In Linux we always execute it
after we have moved the PE to trace prohibited region. So,
we can apply the workaround every time a TSB is executed.

The work around is to issue two TSB consecutively.

NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying
that a late CPU could be blocked from booting if it is the
first CPU that requires the workaround. This is because we
do not allow setting a cpu_hwcaps after the SMP boot. The
other alternative is to use "this_cpu_has_cap()" instead
of the faster system wide check, which may be a bit of an
overhead, given we may have to do this in nvhe KVM host
before a guest entry.

Bug: 213931796
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20211019163153.3692640-4-suzuki.poulose@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit fa82d0b4b833790ac4572377fb777dcea24a9d69)
[Fix conflict due to another workaround that is not backported
(TRBE_OVERWRITE). Also manually update cpucaps.h which is autogenerated
in upstream from arch/arm64/tools/cpucaps which we ignored as part of
the conflict resolution]
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I6b40eaa0ac14552c867860133a04619cb556bc31
2022-01-24 20:34:21 +00:00
Will Deacon
b8e52f4e66 UPSTREAM: arm64: spectre: Consolidate spectre-v3a detection
The spectre-v3a mitigation is split between cpu_errata.c and spectre.c,
with the former handling detection of the problem and the latter handling
enabling of the workaround.

Move the detection logic alongside the enabling logic, like we do for the
other spectre mitigations.

Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Quentin Perret <qperret@google.com>
Link: https://lore.kernel.org/r/20201113113847.21619-10-will@kernel.org
(cherry picked from commit cd1f56b930e857c170d8a04f0f989bfb8a1b5ac1)
Signed-off-by: Will Deacon <willdeacon@google.com>
Change-Id: I01c54f09a8491c883666935bed50476c2f694823
Bug: 178098380
Test: atest VirtualizationHostTestCases on an EL2-enabled device
2021-01-28 17:57:08 +00:00
Will Deacon
1be38826f6 UPSTREAM: arm64: spectre: Rename ARM64_HARDEN_EL2_VECTORS to ARM64_SPECTRE_V3A
Since ARM64_HARDEN_EL2_VECTORS is really a mitigation for Spectre-v3a,
rename it accordingly for consistency with the v2 and v4 mitigation.

Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Quentin Perret <qperret@google.com>
Link: https://lore.kernel.org/r/20201113113847.21619-9-will@kernel.org
(cherry picked from commit c4792b6dbc5070fe67f4cdcfdad39416333acbe0)
Signed-off-by: Will Deacon <willdeacon@google.com>
Change-Id: I6c026fa775b858cca5360aeabb25aeab209f72f7
Bug: 178098380
Test: atest VirtualizationHostTestCases on an EL2-enabled device
2021-01-28 17:57:08 +00:00
Will Deacon
faa4815997 BACKPORT: KVM: arm64: Allocate hyp vectors statically
The EL2 vectors installed when a guest is running point at one of the
following configurations for a given CPU:

  - Straight at __kvm_hyp_vector
  - A trampoline containing an SMC sequence to mitigate Spectre-v2 and
    then a direct branch to __kvm_hyp_vector
  - A dynamically-allocated trampoline which has an indirect branch to
    __kvm_hyp_vector
  - A dynamically-allocated trampoline containing an SMC sequence to
    mitigate Spectre-v2 and then an indirect branch to __kvm_hyp_vector

The indirect branches mean that VA randomization at EL2 isn't trivially
bypassable using Spectre-v3a (where the vector base is readable by the
guest).

Rather than populate these vectors dynamically, configure everything
statically and use an enumerated type to identify the vector "slot"
corresponding to one of the configurations above. This both simplifies
the code, but also makes it much easier to implement at EL2 later on.

Signed-off-by: Will Deacon <will@kernel.org>
[maz: fixed double call to kvm_init_vector_slots() on nVHE]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Quentin Perret <qperret@google.com>
Link: https://lore.kernel.org/r/20201113113847.21619-8-will@kernel.org
(cherry picked from commit b881cdce77b48bd488f268041f32951bab89bb0f)
[will: fixed hyp/Makefile conflict with LTO+CFI flags]
Signed-off-by: Will Deacon <willdeacon@google.com>
Change-Id: I72ae8cfefa18c318bd69de986923e05159e64df4
Bug: 178098380
Test: atest VirtualizationHostTestCases on an EL2-enabled device
2021-01-28 17:57:07 +00:00
Konrad Dybcio
23c2164160 arm64: cpu_errata: Apply Erratum 845719 to KRYO2XX Silver
QCOM KRYO2XX Silver cores are Cortex-A53 based and are
susceptible to the 845719 erratum. Add them to the lookup
list to apply the erratum.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20201104232218.198800-5-konrad.dybcio@somainline.org
Signed-off-by: Will Deacon <will@kernel.org>
2020-11-13 09:47:08 +00:00
Rob Herring
96d389ca10 arm64: Add workaround for Arm Cortex-A77 erratum 1508412
On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load
and a store exclusive or PAR_EL1 read can cause a deadlock.

The workaround requires a DMB SY before and after a PAR_EL1 register
read. In addition, it's possible an interrupt (doing a device read) or
KVM guest exit could be taken between the DMB and PAR read, so we
also need a DMB before returning from interrupt and before returning to
a guest.

A deadlock is still possible with the workaround as KVM guests must also
have the workaround. IOW, a malicious guest can deadlock an affected
systems.

This workaround also depends on a firmware counterpart to enable the h/w
to insert DMB SY after load and store exclusive instructions. See the
errata document SDEN-1152370 v10 [1] for more information.

[1] https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Julien Thierry <julien.thierry.kdev@gmail.com>
Cc: kvmarm@lists.cs.columbia.edu
Link: https://lore.kernel.org/r/20201028182839.166037-2-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2020-10-29 12:56:01 +00:00
Linus Torvalds
6734e20e39 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon:
 "There's quite a lot of code here, but much of it is due to the
  addition of a new PMU driver as well as some arm64-specific selftests
  which is an area where we've traditionally been lagging a bit.

  In terms of exciting features, this includes support for the Memory
  Tagging Extension which narrowly missed 5.9, hopefully allowing
  userspace to run with use-after-free detection in production on CPUs
  that support it. Work is ongoing to integrate the feature with KASAN
  for 5.11.

  Another change that I'm excited about (assuming they get the hardware
  right) is preparing the ASID allocator for sharing the CPU page-table
  with the SMMU. Those changes will also come in via Joerg with the
  IOMMU pull.

  We do stray outside of our usual directories in a few places, mostly
  due to core changes required by MTE. Although much of this has been
  Acked, there were a couple of places where we unfortunately didn't get
  any review feedback.

  Other than that, we ran into a handful of minor conflicts in -next,
  but nothing that should post any issues.

  Summary:

   - Userspace support for the Memory Tagging Extension introduced by
     Armv8.5. Kernel support (via KASAN) is likely to follow in 5.11.

   - Selftests for MTE, Pointer Authentication and FPSIMD/SVE context
     switching.

   - Fix and subsequent rewrite of our Spectre mitigations, including
     the addition of support for PR_SPEC_DISABLE_NOEXEC.

   - Support for the Armv8.3 Pointer Authentication enhancements.

   - Support for ASID pinning, which is required when sharing
     page-tables with the SMMU.

   - MM updates, including treating flush_tlb_fix_spurious_fault() as a
     no-op.

   - Perf/PMU driver updates, including addition of the ARM CMN PMU
     driver and also support to handle CPU PMU IRQs as NMIs.

   - Allow prefetchable PCI BARs to be exposed to userspace using normal
     non-cacheable mappings.

   - Implementation of ARCH_STACKWALK for unwinding.

   - Improve reporting of unexpected kernel traps due to BPF JIT
     failure.

   - Improve robustness of user-visible HWCAP strings and their
     corresponding numerical constants.

   - Removal of TEXT_OFFSET.

   - Removal of some unused functions, parameters and prototypes.

   - Removal of MPIDR-based topology detection in favour of firmware
     description.

   - Cleanups to handling of SVE and FPSIMD register state in
     preparation for potential future optimisation of handling across
     syscalls.

   - Cleanups to the SDEI driver in preparation for support in KVM.

   - Miscellaneous cleanups and refactoring work"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (148 commits)
  Revert "arm64: initialize per-cpu offsets earlier"
  arm64: random: Remove no longer needed prototypes
  arm64: initialize per-cpu offsets earlier
  kselftest/arm64: Check mte tagged user address in kernel
  kselftest/arm64: Verify KSM page merge for MTE pages
  kselftest/arm64: Verify all different mmap MTE options
  kselftest/arm64: Check forked child mte memory accessibility
  kselftest/arm64: Verify mte tag inclusion via prctl
  kselftest/arm64: Add utilities and a test to validate mte memory
  perf: arm-cmn: Fix conversion specifiers for node type
  perf: arm-cmn: Fix unsigned comparison to less than zero
  arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
  arm64: mm: Make flush_tlb_fix_spurious_fault() a no-op
  arm64: Add support for PR_SPEC_DISABLE_NOEXEC prctl() option
  arm64: Pull in task_stack_page() to Spectre-v4 mitigation code
  KVM: arm64: Allow patching EL2 vectors even with KASLR is not enabled
  arm64: Get rid of arm64_ssbd_state
  KVM: arm64: Convert ARCH_WORKAROUND_2 to arm64_get_spectre_v4_state()
  KVM: arm64: Get rid of kvm_arm_have_ssbd()
  KVM: arm64: Simplify handling of ARCH_WORKAROUND_2
  ...
2020-10-12 10:00:51 -07:00
Marc Zyngier
31c84d6c9c arm64: Get rid of arm64_ssbd_state
Out with the old ghost, in with the new...

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:17 +01:00
Marc Zyngier
29e8910a56 KVM: arm64: Simplify handling of ARCH_WORKAROUND_2
Owing to the fact that the host kernel is always mitigated, we can
drastically simplify the WA2 handling by keeping the mitigation
state ON when entering the guest. This means the guest is either
unaffected or not mitigated.

This results in a nice simplification of the mitigation space,
and the removal of a lot of code that was never really used anyway.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:16 +01:00
Will Deacon
c28762070c arm64: Rewrite Spectre-v4 mitigation code
Rewrite the Spectre-v4 mitigation handling code to follow the same
approach as that taken by Spectre-v2.

For now, report to KVM that the system is vulnerable (by forcing
'ssbd_state' to ARM64_SSBD_UNKNOWN), as this will be cleared up in
subsequent steps.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:16 +01:00
Will Deacon
9b0955baa4 arm64: Rename ARM64_SSBD to ARM64_SPECTRE_V4
In a similar manner to the renaming of ARM64_HARDEN_BRANCH_PREDICTOR
to ARM64_SPECTRE_V2, rename ARM64_SSBD to ARM64_SPECTRE_V4. This isn't
_entirely_ accurate, as we also need to take into account the interaction
with SSBS, but that will be taken care of in subsequent patches.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:16 +01:00
Will Deacon
d4647f0a2a arm64: Rewrite Spectre-v2 mitigation code
The Spectre-v2 mitigation code is pretty unwieldy and hard to maintain.
This is largely due to it being written hastily, without much clue as to
how things would pan out, and also because it ends up mixing policy and
state in such a way that it is very difficult to figure out what's going
on.

Rewrite the Spectre-v2 mitigation so that it clearly separates state from
policy and follows a more structured approach to handling the mitigation.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:15 +01:00
Will Deacon
455697adef arm64: Introduce separate file for spectre mitigations and reporting
The spectre mitigation code is spread over a few different files, which
makes it both hard to follow, but also hard to remove it should we want
to do that in future.

Introduce a new file for housing the spectre mitigations, and populate
it with the spectre-v1 reporting code to start with.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:15 +01:00
Will Deacon
688f1e4b6d arm64: Rename ARM64_HARDEN_BRANCH_PREDICTOR to ARM64_SPECTRE_V2
For better or worse, the world knows about "Spectre" and not about
"Branch predictor hardening". Rename ARM64_HARDEN_BRANCH_PREDICTOR to
ARM64_SPECTRE_V2 as part of moving all of the Spectre mitigations into
their own little corner.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:15 +01:00
Will Deacon
b181048f41 KVM: arm64: Simplify install_bp_hardening_cb()
Use is_hyp_mode_available() to detect whether or not we need to patch
the KVM vectors for branch hardening, which avoids the need to take the
vector pointers as parameters.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:15 +01:00
Will Deacon
5359a87d5b KVM: arm64: Replace CONFIG_KVM_INDIRECT_VECTORS with CONFIG_RANDOMIZE_BASE
The removal of CONFIG_HARDEN_BRANCH_PREDICTOR means that
CONFIG_KVM_INDIRECT_VECTORS is synonymous with CONFIG_RANDOMIZE_BASE,
so replace it.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:15 +01:00
Will Deacon
6e5f092784 arm64: Remove Spectre-related CONFIG_* options
The spectre mitigations are too configurable for their own good, leading
to confusing logic trying to figure out when we should mitigate and when
we shouldn't. Although the plethora of command-line options need to stick
around for backwards compatibility, the default-on CONFIG options that
depend on EXPERT can be dropped, as the mitigations only do anything if
the system is vulnerable, a mitigation is available and the command-line
hasn't disabled it.

Remove CONFIG_HARDEN_BRANCH_PREDICTOR and CONFIG_ARM64_SSBD in favour of
enabling this code unconditionally.

Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:15 +01:00
Marc Zyngier
39533e1206 arm64: Run ARCH_WORKAROUND_2 enabling code on all CPUs
Commit 606f8e7b27 ("arm64: capabilities: Use linear array for
detection and verification") changed the way we deal with per-CPU errata
by only calling the .matches() callback until one CPU is found to be
affected. At this point, .matches() stop being called, and .cpu_enable()
will be called on all CPUs.

This breaks the ARCH_WORKAROUND_2 handling, as only a single CPU will be
mitigated.

In order to address this, forcefully call the .matches() callback from a
.cpu_enable() callback, which brings us back to the original behaviour.

Fixes: 606f8e7b27 ("arm64: capabilities: Use linear array for detection and verification")
Cc: <stable@vger.kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
2020-09-29 16:08:03 +01:00
Marc Zyngier
18fce56134 arm64: Run ARCH_WORKAROUND_1 enabling code on all CPUs
Commit 73f3816609 ("arm64: Advertise mitigation of Spectre-v2, or lack
thereof") changed the way we deal with ARCH_WORKAROUND_1, by moving most
of the enabling code to the .matches() callback.

This has the unfortunate effect that the workaround gets only enabled on
the first affected CPU, and no other.

In order to address this, forcefully call the .matches() callback from a
.cpu_enable() callback, which brings us back to the original behaviour.

Fixes: 73f3816609 ("arm64: Advertise mitigation of Spectre-v2, or lack thereof")
Cc: <stable@vger.kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
2020-09-21 18:31:09 +01:00
Marc Zyngier
b11483ef5a arm64: Make use of ARCH_WORKAROUND_1 even when KVM is not enabled
We seem to be pretending that we don't have any firmware mitigation
when KVM is not compiled in, which is not quite expected.

Bring back the mitigation in this case.

Fixes: 4db61fef16 ("arm64: kvm: Modernize __smccc_workaround_1_smc_start annotations")
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
2020-09-21 18:31:09 +01:00
Marc Zyngier
ed888cb0d1 arm64: Allow CPUs unffected by ARM erratum 1418040 to come in late
Now that we allow CPUs affected by erratum 1418040 to come in late,
this prevents their unaffected sibblings from coming in late (or
coming back after a suspend or hotplug-off, which amounts to the
same thing).

To allow this, we need to add ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU,
which amounts to set .type to ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE.

Fixes: bf87bb0881 ("arm64: Allow booting of late CPUs affected by erratum 1418040")
Reported-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20200911181611.2073183-1-maz@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-09-13 13:18:10 +01:00
Marc Zyngier
bf87bb0881 arm64: Allow booting of late CPUs affected by erratum 1418040
As we can now switch from a system that isn't affected by 1418040
to a system that globally is affected, let's allow affected CPUs
to come in at a later time.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20200731173824.107480-3-maz@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-08-21 11:39:56 +01:00
Paolo Bonzini
0378daef0c Merge tag 'kvmarm-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-next-5.6
KVM/arm64 updates for Linux 5.9:

- Split the VHE and nVHE hypervisor code bases, build the EL2 code
  separately, allowing for the VHE code to now be built with instrumentation

- Level-based TLB invalidation support

- Restructure of the vcpu register storage to accomodate the NV code

- Pointer Authentication available for guests on nVHE hosts

- Simplification of the system register table parsing

- MMU cleanups and fixes

- A number of post-32bit cleanups and other fixes
2020-08-09 12:58:23 -04:00
Marc Zyngier
a394cf6e85 Merge branch 'kvm-arm64/misc-5.9' into kvmarm-master/next-WIP
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-07-28 16:26:16 +01:00
David Brazdil
a59a2edbbb KVM: arm64: Substitute RANDOMIZE_BASE for HARDEN_EL2_VECTORS
The HARDEN_EL2_VECTORS config maps vectors at a fixed location on cores which
are susceptible to Spector variant 3a (A57, A72) to prevent defeating hyp
layout randomization by leaking the value of VBAR_EL2.

Since this feature is only applicable when EL2 layout randomization is enabled,
unify both behind the same RANDOMIZE_BASE Kconfig. Majority of code remains
conditional on a capability selected for the affected cores.

Signed-off-by: David Brazdil <dbrazdil@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200721094445.82184-3-dbrazdil@google.com
2020-07-28 10:41:11 +01:00
Florian Fainelli
09c717c92b arm64: Add missing sentinel to erratum_1463225
When the erratum_1463225 array was introduced a sentinel at the end was
missing thus causing a KASAN: global-out-of-bounds in
is_affected_midr_range_list on arm64 error.

Fixes: a9e821b89d ("arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/linux-arm-kernel/CA+G9fYs3EavpU89-rTQfqQ9GgxAMgMAk7jiiVrfP0yxj5s+Q6g@mail.gmail.com/
Link: https://lore.kernel.org/r/20200709051345.14544-1-f.fainelli@gmail.com
Signed-off-by: Will Deacon <will@kernel.org>
2020-07-09 09:42:24 +01:00
Sai Prakash Ranjan
9b23d95c53 arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718
KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
erratum 1530923 and 1024718, so add them to the respective list.
The variant and revision bits are implementation defined and are
different from the their Cortex CPU counterparts on which they are
based on, i.e., r1p0 is equivalent to rdpe.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/7013e8a3f857ca7e82863cc9e34a614293d7f80c.1593539394.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Will Deacon <will@kernel.org>
2020-07-03 16:39:16 +01:00
Sai Prakash Ranjan
a9e821b89d arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040
KRYO4XX gold/big CPU core revisions r0p0 to r3p1 are affected by
erratum 1463225 and 1418040, so add them to the respective list.
The variant and revision bits are implementation defined and are
different from the their Cortex CPU counterparts on which they are
based on, i.e., (r0p0 to r3p1) is equivalent to (rcpe to rfpf).

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/83780e80c6377c12ca51b5d53186b61241685e49.1593539394.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Will Deacon <will@kernel.org>
2020-07-03 16:39:16 +01:00
Sai Prakash Ranjan
108447fd0d arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
Cortex-A55 and are SSB safe, hence add them to SSB
safelist -> arm64_ssb_cpus[].

Reported-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200625103123.7240-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Will Deacon <will@kernel.org>
2020-06-25 20:18:57 +01:00
Linus Torvalds
039aeb9deb Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Paolo Bonzini:
 "ARM:
   - Move the arch-specific code into arch/arm64/kvm

   - Start the post-32bit cleanup

   - Cherry-pick a few non-invasive pre-NV patches

  x86:
   - Rework of TLB flushing

   - Rework of event injection, especially with respect to nested
     virtualization

   - Nested AMD event injection facelift, building on the rework of
     generic code and fixing a lot of corner cases

   - Nested AMD live migration support

   - Optimization for TSC deadline MSR writes and IPIs

   - Various cleanups

   - Asynchronous page fault cleanups (from tglx, common topic branch
     with tip tree)

   - Interrupt-based delivery of asynchronous "page ready" events (host
     side)

   - Hyper-V MSRs and hypercalls for guest debugging

   - VMX preemption timer fixes

  s390:
   - Cleanups

  Generic:
   - switch vCPU thread wakeup from swait to rcuwait

  The other architectures, and the guest side of the asynchronous page
  fault work, will come next week"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (256 commits)
  KVM: selftests: fix rdtsc() for vmx_tsc_adjust_test
  KVM: check userspace_addr for all memslots
  KVM: selftests: update hyperv_cpuid with SynDBG tests
  x86/kvm/hyper-v: Add support for synthetic debugger via hypercalls
  x86/kvm/hyper-v: enable hypercalls regardless of hypercall page
  x86/kvm/hyper-v: Add support for synthetic debugger interface
  x86/hyper-v: Add synthetic debugger definitions
  KVM: selftests: VMX preemption timer migration test
  KVM: nVMX: Fix VMX preemption timer migration
  x86/kvm/hyper-v: Explicitly align hcall param for kvm_hyperv_exit
  KVM: x86/pmu: Support full width counting
  KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in
  KVM: x86: announce KVM_FEATURE_ASYNC_PF_INT
  KVM: x86: acknowledgment mechanism for async pf page ready notifications
  KVM: x86: interrupt based APF 'page ready' event delivery
  KVM: introduce kvm_read_guest_offset_cached()
  KVM: rename kvm_arch_can_inject_async_page_present() to kvm_arch_can_dequeue_async_page_present()
  KVM: x86: extend struct kvm_vcpu_pv_apf_data with token info
  Revert "KVM: async_pf: Fix #DF due to inject "Page not Present" and "Page Ready" exceptions simultaneously"
  KVM: VMX: Replace zero-length array with flexible-array
  ...
2020-06-03 15:13:47 -07:00
Will Deacon
c350717ec7 Merge branch 'for-next/kvm/errata' into for-next/core
KVM CPU errata rework
(Andrew Scull and Marc Zyngier)
* for-next/kvm/errata:
  KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
  arm64: Unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE}
2020-05-28 18:02:51 +01:00
Will Deacon
d82755b2e7 KVM: arm64: Kill off CONFIG_KVM_ARM_HOST
CONFIG_KVM_ARM_HOST is just a proxy for CONFIG_KVM, so remove it in favour
of the latter.

Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200505154520.194120-2-tabba@google.com
2020-05-16 15:04:18 +01:00
Geert Uytterhoeven
357dd8a2af arm64: cpufeature: Add "or" to mitigations for multiple errata
Several actions are not mitigations for a single erratum, but for
multiple errata.  However, printing a line like

    CPU features: detected: ARM errata 1165522, 1530923

may give the false impression that all three listed errata have been
detected.  This can confuse the user, who may think his Cortex-A55 is
suddenly affected by a Cortex-A76 erratum.

Add "or" to all descriptions for mitigations for multiple errata, to
make it clear that only one or more of the errata printed are
applicable, and not necessarily all of them.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200512145255.5520-1-geert+renesas@glider.be
Signed-off-by: Will Deacon <will@kernel.org>
2020-05-12 18:37:13 +01:00
Andrew Scull
02ab1f5018 arm64: Unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE}
Errata 1165522, 1319367 and 1530923 each allow TLB entries to be
allocated as a result of a speculative AT instruction. In order to
avoid mandating VHE on certain affected CPUs, apply the workaround to
both the nVHE and the VHE case for all affected CPUs.

Signed-off-by: Andrew Scull <ascull@google.com>
Acked-by: Will Deacon <will@kernel.org>
CC: Marc Zyngier <maz@kernel.org>
CC: James Morse <james.morse@arm.com>
CC: Suzuki K Poulose <suzuki.poulose@arm.com>
CC: Will Deacon <will@kernel.org>
CC: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20200504094858.108917-1-ascull@google.com
Signed-off-by: Will Deacon <will@kernel.org>
2020-05-04 16:05:47 +01:00
Nathan Chancellor
9a25136a61 arm64: Mark call_smc_arch_workaround_1 as __maybe_unused
When building allnoconfig:

arch/arm64/kernel/cpu_errata.c:174:13: warning: unused function
'call_smc_arch_workaround_1' [-Wunused-function]
static void call_smc_arch_workaround_1(void)
            ^
1 warning generated.

Follow arch/arm and mark this function as __maybe_unused.

Fixes: 4db61fef16 ("arm64: kvm: Modernize __smccc_workaround_1_smc_start annotations")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-11 12:01:59 +00:00
Mark Brown
4db61fef16 arm64: kvm: Modernize __smccc_workaround_1_smc_start annotations
In an effort to clarify and simplify the annotation of assembly functions
in the kernel new macros have been introduced. These replace ENTRY and
ENDPROC with separate annotations for standard C callable functions,
data and code with different calling conventions.

Using these for __smccc_workaround_1_smc is more involved than for most
symbols as this symbol is annotated quite unusually, rather than just have
the explicit symbol we define _start and _end symbols which we then use to
compute the length. This does not play at all nicely with the new style
macros. Instead define a constant for the size of the function and use that
in both the C code and for .org based size checks in the assembly code.

Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
2020-03-09 17:35:43 +00:00
Mark Brown
6e52aab901 arm64: kvm: Modernize annotation for __bp_harden_hyp_vecs
We have recently introduced new macros for annotating assembly symbols
for things that aren't C functions, SYM_CODE_START() and SYM_CODE_END(),
in an effort to clarify and simplify our annotations of assembly files.

Using these for __bp_harden_hyp_vecs is more involved than for most symbols
as this symbol is annotated quite unusually as rather than just have the
explicit symbol we define _start and _end symbols which we then use to
compute the length. This does not play at all nicely with the new style
macros. Since the size of the vectors is a known constant which won't vary
the simplest thing to do is simply to drop the separate _start and _end
symbols and just use a #define for the size.

Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
2020-03-09 17:35:35 +00:00
Will Deacon
ab3906c531 Merge branch 'for-next/errata' into for-next/core
* for-next/errata: (3 commits)
  arm64: Workaround for Cortex-A55 erratum 1530923
  ...
2020-01-22 11:35:05 +00:00
Sai Prakash Ranjan
83b0c36b8a arm64: Add KRYO{3,4}XX CPU cores to spectre-v2 safe list
The "silver" KRYO3XX and KRYO4XX CPU cores are not affected by Spectre
variant 2. Add them to spectre_v2 safe list to correct the spurious
ARM_SMCCC_ARCH_WORKAROUND_1 warning and vulnerability status reported
under sysfs.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
[will: tweaked commit message to remove stale mention of "gold" cores]
Signed-off-by: Will Deacon <will@kernel.org>
2020-01-17 12:46:41 +00:00
Steven Price
275fa0ea2c arm64: Workaround for Cortex-A55 erratum 1530923
Cortex-A55 erratum 1530923 allows TLB entries to be allocated as a
result of a speculative AT instruction. This may happen in the middle of
a guest world switch while the relevant VMSA configuration is in an
inconsistent state, leading to erroneous content being allocated into
TLBs.

The same workaround as is used for Cortex-A76 erratum 1165522
(WORKAROUND_SPECULATIVE_AT_VHE) can be used here. Note that this
mandates the use of VHE on affected parts.

Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16 10:44:14 +00:00